Addition of pre-last transfer acknowledge signal to bus interfac

Details Addition of pre-last transfer acknowledge signal to bus interfac Addition of pre-last transfer acknowledge signal to bus interfac

1996-01-18

1997-06-17

An, Meng-ai T.

395855, 395856, 395860, 395741, G06F 1300

Patent

active

056405189

ABSTRACT:
A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system's bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.

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"Disk Performance Improvement Through Transfer Rate Mismatch Compensation" IBM Technical Disclosure Bulletin, V30 N12, dtd May 1988, pp. 390-393.
"Automatic Bus Pacing on a Micro Channel", IBM Technical Disclosure Bulletin, V33 N3B, dtd Aug. 1990, pp. 258-261.
Motorola "PowerPC 601, RISC Microprocessor User's Manual", Chapters 8 and 9 .

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