Addition circuit for accumulating redundant binary numbers

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S709000

Reexamination Certificate

active

07085797

ABSTRACT:
An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition circuit further includes a 4:3 compression adder for receiving each of the sparse carry-save fields of the four redundant binary numbers, and producing a second sum field therefrom. The addition circuit also includes a 3:2 compression adder for receiving the first sum field, the first carry field and the second sum field, and producing a third sum field and a second carry field therefrom. The third sum field and the second carry field are the final results from addition of the four redundant binary numbers.

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Wang, Z. et al. “New Concepts for the Design of Carry Lookahead Adders,” Proceedings of the International Symposium on Circuits and Systems. (ISCS). Chicago, May 3-6, 1993, New York, IEEE, US, vol. 2, pp. 1837-1840.

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