Adder with intermediate carry circuit

Details Adder with intermediate carry circuit Adder with intermediate carry circuit

1988-12-16

1992-08-04

Mai, Tan V.

Boots, shoes, and leggings

364788, G06F 750

Patent

active

051365391

ABSTRACT:
An metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals. For a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.

REFERENCES:
patent: 3100836 (1963-08-01), Paul et al.
patent: 3553446 (1971-01-01), Kruy
patent: 4584661 (1986-04-01), Grundland
patent: 4623982 (1986-11-01), Ware
patent: 4639888 (1987-01-01), Nussbaecher
patent: 4811272 (1989-03-01), Wolrich et al.

Affiliated with

Also associated with

Rating

Adder with intermediate carry circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adder with intermediate carry circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adder with intermediate carry circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-784504