Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2005-06-28
2005-06-28
Chaki, Kakali (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06912560
ABSTRACT:
An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at least one of the stages and is operative to generate an overflow flag for the adder substantially in parallel with the generation of the sum output signal and the primary carry-output signal of the adder. Advantageously, the invention substantially reduces the computational delay associated with generation of the overflow flag, relative to that of conventional adders, without requiring an increase in transistor count or circuit area.
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Agere Systems Inc.
Chaki Kakali
Do Chat C.
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