Adder which employs both carry look-ahead and carry select techn

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Details

364488, 364785, 36478601, 36478701, G06F 1750, G06F 750

Patent

active

058985964

ABSTRACT:
The hybrid adder of the present invention uses stages of carry select functions to provide serial carries and a carry look-ahead tree structure to compute the final carries in parallel. The longer the carry select stages become, the slower and smaller the hybrid adder gets by reducing the size of the carry tree. By making the carry select stages shorter, the faster and larger the adder gets by increasing the size of the carry tree. The increased flexibility of the resulting hybrid adder gives the circuit designer a greater range of possible designs to achieve optimum size and speed performance. A preferred process for selecting optimum stage lengths is also described. The method for designing the hybrid adder is preferably carried out using a logic synthesis software program.

REFERENCES:
patent: 5208769 (1993-05-01), Mandava
patent: 5229959 (1993-07-01), Scriber et al.
patent: 5272662 (1993-12-01), Scriber et al.
patent: 5285406 (1994-02-01), Lynch et al.
patent: 5377122 (1994-12-01), Werner et al.
patent: 5508952 (1996-04-01), Kantabutra
patent: 5638313 (1997-06-01), Chu

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