Adder using multi-state logic

Details Adder using multi-state logic Adder using multi-state logic

1988-08-24

1990-04-10

Clark, David L.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

049166530

ABSTRACT:
A binary digital full adder as a component element of a digital circuit receives three binary signals including two input signals and a carry-in from the lower digit. The adder comprises a four-state logic converter for adding together the three binary signals in terms of current addition to convert the sum into a four-state logic signal, and an encoder for deciding a four-state logic level to encode it into a binary sum and a carry-out.

REFERENCES:
patent: 4254471 (1981-03-01), Hunt
patent: 4471454 (1984-09-01), Dearden et al.
patent: 4689763 (1987-08-01), Fang
patent: 4701877 (1987-10-01), Sahoda et al.
patent: 4718035 (1988-01-01), Hara et al.
patent: 4733365 (1988-03-01), Nagamatsu
patent: 4740907 (1988-04-01), Shimizu et al.
patent: 4831579 (1989-05-01), Hara et al.

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