Adder, multiplier and integrated circuit

Details Adder, multiplier and integrated circuit Adder, multiplier and integrated circuit

2007-01-02

2007-01-02

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S620000

Reexamination Certificate

active

10648373

ABSTRACT:
An adder includes a first XOR element for generating an XOR output of the first and the second data inputs, a first multiplexer for selecting one of the first carry input or the first data input while the XOR output is made a selection signal, a second multiplexer for selecting one of the second carry input or the second data input, a third multiplexer for selecting one of the first or the second carry inputs while the carry selection input is made a selection signal, and a second XOR element for generating an XOR output of an output of the third multiplexer and the XOR output, and is characterized in that an output of the first multiplexer is made a first carry output, an output of the second multiplexer is made a second carry output, and an output of the third multiplexer is made an addition value.

REFERENCES:
patent: 4675837 (1987-06-01), Ulbrich et al.
patent: 4707800 (1987-11-01), Montrone et al.
patent: 5027311 (1991-06-01), Zion
patent: 5337269 (1994-08-01), McMahan et al.
patent: 5581497 (1996-12-01), Kumar
patent: 5875123 (1999-02-01), Dao Trong et al.
patent: 5898596 (1999-04-01), Ruetz
patent: 6199091 (2001-03-01), Kobayashi et al.

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