Adder having means for reducing propagation time of carry bit

Details Adder having means for reducing propagation time of carry bit Adder having means for reducing propagation time of carry bit

1988-08-25

1990-08-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

049492977

ABSTRACT:
An adder has first through third switching circuits, a logic circuit and an adding circuit part. The first switching circuit is coupled between a carry bit input terminal and a carry bit output terminal. The second switching circuit is coupled between a first power source voltage and the carry bit output terminal, and the third switching circuit is coupled between a second power source voltage and the carry bit output terminal. The logic circuit controls the ON/OFF states of the first through third switching circuits so that only one switching circuit is turned ON responsive to two binary values which are to be added in the adding circuit part. The propagation time of a carry bit signal from the carry bit input terminal to the carry bit output terminal is constant regardless of the number of bits of the adding circuit part.

REFERENCES:
patent: 4425623 (1984-01-01), Russell
patent: 4464729 (1984-08-01), Mlynek
patent: 4504924 (1985-03-01), Cook et al.
patent: 4584660 (1986-04-01), Young et al.
patent: 4817031 (1989-03-01), Tokumaru

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