Adder for floating point data suitable for digital signal proces

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G06F 750

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active

045920060

ABSTRACT:
In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.

REFERENCES:
patent: 4366548 (1982-12-01), Kregness et al.
patent: 4429370 (1984-01-01), Blau et al.
Smith et al., "Fixed-Point, Floating-Point Adder", Technical Notes--A publication of RCA/Princeton, N.J. in No. 846, 3 sheets, Oct. 8, 1969.
Hale et al., "Biased and Non-Biased Binary Conversion and Exponent Under/Over Flow Detection", IBM Tech. Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 252-254.

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