Adder control method and adder control circuit

Details Adder control method and adder control circuit Adder control method and adder control circuit

1990-03-28

1991-11-12

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

Patent

active

050653539

ABSTRACT:
In an adder control circuit, a plurality of full adders are so arranged that a carry bit of the full adder for calculating low orders of values to be added is inputted to the full adder for calculating high orders thereof. In this case, the addresses are controlled in response to a clock having a time period which is more than a maximum calculation time period among calculation time periods by the respective full adders required for outputting the carry bits, and is less than a total calculation time period of all full adders.

REFERENCES:
patent: 3932734 (1976-01-01), Parsons
patent: 4357675 (1982-11-01), Freyman
patent: 4536855 (1985-08-01), Morton
patent: 4683548 (1987-07-01), Mlynek
patent: 4887233 (1989-12-01), Cash et al.
Computer Architecture and Organization, 1978, J. P. Hayes, pp. 171-179.

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