Adder circuitry utilizing redundant signed digit operands

Details Adder circuitry utilizing redundant signed digit operands Adder circuitry utilizing redundant signed digit operands

1987-08-18

1989-09-12

Malzahn, David H.

Boots, shoes, and leggings

G06F 749

Patent

active

048666572

ABSTRACT:
A high speed arithmetic processor and adder circuitry thereof are disclosed in which carry (borrow) propagation is never more than one digit. Addition (or subtraction) are performed by: (a) determining an intermediate carry (or borrow) at the i-th order position and an intermediate sum (or difference) at the i-th order position from the addend (or subtrahend) and the augend (or minuend) and (b) determining the sum (or difference) of the intermediate sum (or difference) at the i-th order position and the intermediate carry (or borrow) at the (i-1)-th or next-lower-order position. Logic equations, truth tables and circuitry are disclosed for implementing several embodiments of the invention.

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