Adder circuit incorporating byte boundaries

Details Adder circuit incorporating byte boundaries Adder circuit incorporating byte boundaries

1995-12-22

1998-02-17

Malzahn, David H.

Boots, shoes, and leggings

364749, G06F 750

Patent

active

057198020

ABSTRACT:
In accordance with the present invention, an adder is disclosed which combines byte boundary control signals with propagate-generate signal pairs immediately resulting from bit pairs of the input signals. Combining the byte boundary control signals with the first level propagate-generate signal pairs, rather than combining the byte boundary control signals with propagate-generate signal pairs indicative of the carry-out of a byte, allows the adder to utilize a more efficient tree signal path topology in which multiple levels of circuitry may be eliminated, thereby resulting in a reduction in propagation delay.

REFERENCES:
patent: 4914617 (1990-04-01), Putrino et al.
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5418736 (1995-05-01), Widigen et al.
patent: 5432728 (1995-07-01), Curtet

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