Adder circuit and associated layout structure

Details Adder circuit and associated layout structure Adder circuit and associated layout structure

1997-10-24

2002-11-12

Ngo, Chuong Dinh (Department: 2787)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S710000

Reexamination Certificate

active

06480875

ABSTRACT:

BACKGROUND OF THE PRESENT INVENTION
The present invention relates to an improvement in the adder circuits suitable for LSIs as well as to an improvement in the layout structure of such adder circuits.
In recent years, LSIs have improved in the rate of operation as well as in the level of integration of elements. The speed-up of addition operations in the adder circuits is a great contribution to increasing the rate of LSI operation. Various schemes to implement fast addition operations have been proposed. For instance, adder circuits have been known in the art which employ a carry look ahead (CLA) circuit, one example of which is described below.
In a commonly-used adder circuit having a CLA circuit, at the time two numbers which contain a plurality of digits are added together a carry generation logic gi and a carry propagation logic pi are defined for every i digits, and a block carry propagation logic producing circuit capable of producing a block carry propagation logic and a block carry generation logic producing circuit capable of producing a block carry generation logic are formed by arrangement of gi and pi over a plurality of digits (bits). For example, when an addition operation of numbers A and B formed of n digits is performed, each digit's carry generation and propagation logics gi and pi are given by the following equations.
pi=Ai+Bi
gi=Ai·Bi
Hereinafter, these operators “+”, “·”, and “/” designate logical add, logical product, and logical inversion, respectively. A block carry generation logic G
0
over three digits from digit 2
0
to digit 2
2
is given by the following equation.
G
0=
g
2
+p
2
·g
1
+p
2
·
p
1
·
g
0
  (a)
If this logic G
0
is constructed using CMOS circuits, then a structure, shown in
FIG. 7
, is obtained.
Referring to
FIG. 7
, whereas
501
-
506
are p-type metal-oxide-semiconductor (PMOS) transistors,
507
-
512
are n-type metal-oxide-semiconductor (NMOS) transistors. The source, gate, and drain of PMOS transistor
501
are coupled to VDD (the supply voltage), to the input g
2
, and to the sources of PMOS transistors
502
and
503
, respectively. The gate and drain of PMOS transistor
502
are coupled to the input p
2
and to the sources of PMOS transistors
504
,
505
, and
506
, respectively. The gate and drain of PMOS transistor
503
are coupled to the input g
1
and to the sources of PMOS transistors
504
,
505
, and
506
, respectively. The gate and drain of PMOS transistor
504
are coupled to the input p
1
and to the output node y, respectively. The gate and drain of PMOS transistor
505
are coupled to the input p
2
and to the output node y, respectively. The gate and drain of PMOS transistor
506
are coupled to the input go and to the output node y, respectively.
The source, gate, and drain of NMOS transistor
507
are coupled to GND (ground), to the input g
2
, and to the output node y, respectively. The source, gate, and drain of NMOS transistor
508
are coupled to the drain of NMOS transistor
509
, to the input g
1
, and to the output node y, respectively. The source, gate, and drain of NMOS transistor
509
are coupled to GND, to the input p
2
, and to the source of NMOS transistor
508
, respectively. The source, gate, and drain of NMOS transistor
510
are coupled to the drain of NMOS transistor
511
, to the input g
0
, and to the output node y, respectively. The source, gate, and drain of NMOS transistor
511
are coupled to the drain of NMOS transistor
512
, to the input p
2
, and to the source of NMOS transistor
510
, respectively. The source, gate, and drain of NMOS transistor
512
are coupled to GND, to the input p
1
, and to the source of NMOS transistor
511
.
520
is a connection net for PMOS transistors
501
,
502
, and
503
.
521
is a connection net for PMOS transistors
502
,
503
,
504
,
505
, and
506
.
Referring to
FIG. 7
, a “0” is applied to the output node y if the NMOS transistor logic is g
2
+p
2
·g
1
+p
2
·p
1
·g
0
. In other cases the output node y is placed in the non-drive state.
On the other hand, a “1” is applied to the output node y if the PMOS transistor logic is /g
2
·(/p
2
+/g
1
)·(/p
2
+/p
1
+/g
0
). In other cases, the output node y is placed in the non-drive state. However, the PMOS transistor logic and the NMOS transistor logic are in a complementary relationship and, as a result, the output node y is driven to “0” or to “1”.
A block carry propagation logic P
0
over three digits from digit 2
0
to digit 2
2
is given by the following equation.
P
0
=p
2
·
p
1
·
p
0
  (b)
If this logic P
0
is constructed using CMOS circuits, then a structure, shown in
FIG. 9
, is obtained.
Referring now to
FIG. 9
, whereas
600
-
602
are PMOS transistors,
603
-
605
are NMOS transistors. PMOS transistors
600
-
602
are coupled in parallel with one another. PMOS transistors
600
-
602
each have a terminal that is coupled to VDD and another terminal that is coupled to the output node y. The gate of PMOS transistor
600
is coupled to the input p
0
. The gate of PMOS transistor
601
is coupled to the input p
1
. The gate of PMOS transistor
602
is coupled to the input p
2
. On the other hand, NMOS transistors
603
-
605
are coupled in series with one another. The source and drain of NMOS transistor
605
is coupled to GND and to the source of NMOS transistor
604
, respectively. The drain of NMOS transistor
604
is coupled to the source of NMOS transistor
603
. The drain of NMOS transistor
603
is coupled to the output node y. The gate of NMOS transistor
603
is coupled to the input p
2
. The gate of NMOS transistor
604
is coupled to the input p
1
. The gate of NMOS transistor
605
is coupled to the input p
0
.
Referring to
FIG. 8
, a diagram as a result of laying out the logic of
FIG. 7
is shown.
FIG. 10
shows a diagram as a result of laying out the logic of FIG.
9
. As can be seen from the logic of
FIG. 7
, in the PMOS transistor region two PMOS transistors (PMOS transistors
502
,
503
) are connected in parallel between VDD and the output node y and, in addition, three PMOS transistors (PMOS transistors
504
,
505
,
506
), are also connected in parallel between VDD and the output node y. Because of such arrangement, there is produced the disadvantage that larger source and drain regions are required in the PMOS transistor formation area. This drawback is explained in detail. Referring to the
FIG. 8
layout, the drain region of PMOS transistor
501
and each of the source regions of PMOS transistors
502
and
503
are connected together by the connection net
520
, and each of the drain regions of PMOS transistors
502
and
503
and the source regions of PMOS transistors
504
,
505
, and
506
are connected together by the connection net
521
. Since these connection nets
520
and
521
are connected with a first-level metallic layer, this requires the provision of contact regions
522
and
523
for establishing connections between the connection nets
520
and
521
and the source or drain regions of the foregoing PMOS transistors. The source or drain region of PMOS transistors extends, resulting in an increase in the capacitance and, and the operation delay increases.
As can be seen by reference to
FIG. 7
, formed over and under PMOS transistors
502
and
503
that are parallel-connected are PMOS transistors
501
,
504
,
505
, and
506
. Accordingly, it becomes necessary to divide an OD (oxide diffusion) region into two regions, namely a region
524
and a region
525
. It further becomes necessary to form a free region between the regions
524
and
525
. The size of the adder circuit increases by a proportional amount to such a free region.
On the other hand, in the NMOS transistor region two NMOS transistors, i.e., NMOS transistors
508
and
509
, are connected in series between GND (ground) and the output node y, and, in addition, three NMOS transistors, i.e., NMOS transistors
510
,
511
, and
512
, are also connected in series between GND and the ou

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