Adder circuit

Details Adder circuit Adder circuit

1982-09-03

1986-02-25

Thomas, James D.

Boots, shoes, and leggings

G05F 750

Patent

active

045731373

ABSTRACT:
In an adder circuit in which the input data is divided into a plurality of bit blocks each consisting of a plurality of bits for parallel data processing, two adder sections with the carry inputs thereto respectively set to logic "0" and "1" are provided for each of the blocks other than the LSB block. The sum and carry outputs from each section in each block are commonly connected through a gate circuit, which is controlled by a carry output from the next lower bit block.

REFERENCES:
patent: 3553446 (1971-01-01), Kruy
patent: 3728532 (1973-04-01), Pryor
patent: 3767906 (1973-10-01), Pryor
patent: 4139894 (1979-02-01), Reitsma
Anderson, "Five-Level Combinations Sum Predict and Carry Propagate Adder", IBM Technical Disclosure Bulletin, vol. 14, #1, Jun./1971, pp. 112-113.
"Computer Arithmetic: Principles, Architecture, and Design", K. Hwang, Chapter 3, Sec. 7, Carry-Select Adders, p. 82, FIG. 3.7 (John Wiley & Sons, 1979).

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