Adder cell having a sum part and a carry part

Details Adder cell having a sum part and a carry part Adder cell having a sum part and a carry part

1989-01-12

1990-04-17

Miller, Stanley D.

Boots, shoes, and leggings

364784, 364787, 307443, 307570, G05F 750, H03K 1716

Patent

active

049186400

ABSTRACT:
An adder cell having a sum part and a carry part, whereby the sum part and the carry part each contain differential amplifiers having exclusively bipolar or ECL technology as well as differential amplifiers having mixed bipolar MOS transistors. The processing speed can be considerably increased with such an arrangement in comparison to exclusive CMOS adder cells. Additionally, the adder cell carries out a level conversion of CMOS input levels to ECL output levels, so that CMOS levels between 0 and 5 volts can be received at the first four inputs (E1, E2, E3, E4) and ECL boosts in the millivolt range can be taken at the sum outputs (S, S) or, at the carry outputs (CO, CO).

REFERENCES:
patent: 4718035 (1988-01-01), Hara et al.
patent: 4740907 (1988-04-01), Shimizu et al.
patent: 4831579 (1989-05-01), Hara et al.
H. Weiss et al., "Integrierte MOS-Schaltungen", Springer-Verlag Verlin-Heidelberg--New York (1982) pp. 188 through 194.
Hotta et al., "CMOS/Bipolar Circuits for 60-MHz Digital Processing", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 808-813.

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