Adder cell for carry-save arithmetic

Details Adder cell for carry-save arithmetic Adder cell for carry-save arithmetic

1989-03-17

1990-01-09

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

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active

048932698

ABSTRACT:
An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.

REFERENCES:
patent: 4621338 (1986-11-01), Uhlenhoff
patent: 4713790 (1987-12-01), Kloker et al.
patent: 4730266 (1988-03-01), van Meerbergen et al.
patent: 4733365 (1988-03-01), Nagamatsu
patent: 4839849 (1989-06-01), Knauer
Kai Kwang, "Computer Arithmetic Principles, Architecture, and Design", 1979, pp. 69-127.

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