Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-07-07
2002-05-14
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06389444
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an adder apparatus used in a multiplier of a processor.
2. Description of the Related Art
The above-mentioned multiplier may require an adder apparatus having a function of adding +1 to an input signal and a function of adding +2 to the input signal.
A prior art adder apparatus having the two above-mentioned adding functions adopts a binary look-ahead carry (BLC) array which is constructed by a first adder for adding +1 to an input signal, a second adder for adding +2 to the input signal, and a selector for selecting one of the first and second adders. This will be explained later in detail.
In the above-described prior art adder apparatus, however, since two kinds of adders as well as the selector are required, the circuit configuration is increased in size, which reduces the integration. Also, since a signal path includes the selector, the signal delay is increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a small-sized adder apparatus having a +1 function and +2 function with a small signal delay.
According to the present invention, in an adder apparatus for receiving an n-bit input signal and a control signal to generate an (n+1)-bit output signal, a first logic circuit performs a NOR operation upon a first bit of the n-bit input signal and the control signal to generate a first signal. A second logic circuit performs an OR operation upon the first bit of the n-bit input signal and the control signal to generate a logic OR signal and performs a NAND operation upon the logic OR signal and a second bit of the n-bit input signal to generate a second signal.
Each of third logic circuits performs a NAND operation upon an(i−1)th (i=3, 4, . . . , n) bit of the n-bit input signal and i-th bit of the n-bit input signal to generate a third signal. A carry signal generating circuit receives the first, second and third signals to generate “n” carry signals. A sum generation circuit receives the n-bit input signal, the “n” carry signals and the control signal to generate the (n+1)-bit output signal and includes a fourth logic circuit for performing an exclusive NOR operation upon the first bit of the n-bit input signal and the control signal to generate a first bit of the (n+1)-bit output signal.
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Japanese Office Action, dated May 29, 2001, with English language translation of Japanese Examiner's comments.
T. Inoue et al., “A 300 MHz 16b BICMOS Video Signal Processor”, 1993 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 36-37.
Malzahn David H.
NEC Corporation
Whitham Curtis & Christofferson, P.C.
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