Adder and multiplier circuit employing the same

Details Adder and multiplier circuit employing the same Adder and multiplier circuit employing the same

1994-02-22

1995-06-20

Mai, Tan V.

Boots, shoes, and leggings

364786, G06F 752

Patent

active

054265983

ABSTRACT:
A multiplier circuit has a partial AND generating portion generating n in number of partial AND's as products of a multiplied value and respective bits of n-bit multiplying value, an intermediate sum generating portion inputting n in number of partial AND's, generating intermediate sums and reducing number of the intermediate sums progressively for finally outputting two intermediate sums, and an adder adding two intermediate sums output from the intermediate sum generating portions for outputting a product of multiplication of the multiplied value and the multiplying value. The intermediate sum generating portion has a plurality of intermediate sum calculating circuits, each of which has a plurality of adders of the type of four inputs and two outputs, connected in parallel, the intermediate sum calculating circuits are connected in a plurality of stages in a tree-like configuration.

REFERENCES:
patent: 4901270 (1990-02-01), Galbi et al.
patent: 5210711 (1993-05-01), Rossmere et al.
patent: 5303176 (1994-04-01), Hrusecky et al.
Lai et al., "Logic Network of Carry-Save Adders", IEEE Trans. on Computer, vol. C-31, No. 9, Sep. 1982, pp. 870-882.
Singh et al., "Multiple Operand Addition and Multiplication", IEEE Trans. on Computer, vol. C-22, No. 2, Feb. 1973, pp. 113-120.
Shen et al., "4-2 Carry-Save Adder Implementation Using Send Circuits", IBM Tech. Disclosure Bull. vol. 20, No. 9 Feb. 1978, pp. 3594-3597.
Weinberger, "4-2 Carry-Save Adder Module", IBM Tech. Disclosure Bull. vol. 23, No. 8, Jan. 1981, pp. 3811-3814.

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