Add-on with intermixed pin connection

Details Add-on with intermixed pin connection Add-on with intermixed pin connection

1997-08-06

1999-11-09

Nguyen, Tan T.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

059826533

ABSTRACT:
A substrate with a number of memory chips in a standard arrangement. However, the traces for either or both of data and address lines are intermixed, such that, for example, D0 can be re-routed so that it need not connect to D0 on a particular memory chip. For an add-on card or module with the processor and SRAM on the same card, the connections between the processor pins and the SRAM pins can be intermixed. For a memory add-on card or module, the lines between the module connector and the memory chip pins can be intermixed. Since all of the bits get addressed in any event in each chip, it is transparent to the user that such a re-routing has occurred. Such a re-routing will simplify the trace layout significantly, eliminating required cross-overs.

REFERENCES:
patent: 5557564 (1996-09-01), Haraguchi et al.
patent: 5648679 (1997-07-01), Chillara et al.

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