Add/drop multiplexor with aggregate serializer/deserializers

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C370S539000

Reexamination Certificate

active

10112556

ABSTRACT:
A telecommunications node architecture is disclosed that facilitates the loop-back of a signal in an add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

REFERENCES:
patent: 5265089 (1993-11-01), Yonehara
patent: 5442620 (1995-08-01), Kremer
patent: 5790563 (1998-08-01), Ramamurthy et al.
patent: 5793746 (1998-08-01), Gerstel et al.
patent: 6088371 (2000-07-01), Inada et al.
patent: 6317426 (2001-11-01), Afanador et al.
patent: 6522671 (2003-02-01), Solheim et al.
patent: 6587470 (2003-07-01), Elliot et al.
patent: 6944190 (2005-09-01), Tomar et al.
patent: 2001/0046207 (2001-11-01), Isonuma et al.
patent: 2003/0007513 (2003-01-01), Barker et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Add/drop multiplexor with aggregate serializer/deserializers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Add/drop multiplexor with aggregate serializer/deserializers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Add/drop multiplexor with aggregate serializer/deserializers will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3822583

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.