Add, compare and select circuit

Details Add, compare and select circuit Add, compare and select circuit

1993-12-09

1995-05-02

Envall, Jr., Roy N.

Excavating

341 94, 341107, G06F 1110

Patent

active

054126690

ABSTRACT:
A circuit for minimizing the number of cycles needed to add a first number of quantities together to produce a first result in parallel with the addition of a similar number of quantities to produce a second result, subtracting one result from the other to determine which result is the least, and selecting and storing the least result. For the various additions and the subtraction above named, n bit addends are divided into m upper bits and n-m lower bits. m bit addends (upper bits) are added together separately from and simultaneously with the addition of the n-m bits (lower bits). The first m bit result is subtracted from the second m bit result and the upper bit of that subtraction is adjusted according to the number of carry bits produced by the various lower bit additions and subtraction. In that manner, an accurate comparison of the two m bit results is obtained. A logic array and a mux array provide fast adjustment so that the entire add, compare, and select process is accomplished in one cycle.

REFERENCES:
patent: 4606027 (1986-08-01), Otani
patent: 5027374 (1991-06-01), Rossman
patent: 5081651 (1992-01-01), Kubo
patent: 5181209 (1993-01-01), Hagenauer et al.
patent: 5220570 (1993-06-01), Lou et al.
patent: 5291499 (1994-03-01), Behrens et al.
Fettweis et al. (1991) "High Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture" IEEE Communications Magazine May 1991: 46-55.
Shung et al. (1990) "VLSI Architectures for Metric Normalization in the Viterbi Algorithm" IEEE pp. 1723-1728.

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