ADC background calibration timing

Details ADC background calibration timing ADC background calibration timing

2007-05-29

2007-05-29

Barnie, Rexford (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000

Reexamination Certificate

active

11162463

ABSTRACT:
A background calibrating, skip and fill, analog/digital converter (ADC) generates an output data sequence having successive data elements representing magnitudes of successive samples of an analog input signal (X) acquired during successive cycles of a clock signal. The ADC normally samples the analog input signal during most clock cycles, but occasionally executes a calibration cycle in which it samples a reference signal of known magnitude, determines the error in its output data, and calibrates itself to eliminate the error. The ADC calculates a magnitude of data elements of the output sequence corresponding to samples of the input signal that were skipped during a calibration cycle by interpolating preceding and succeeding sample values. The ADC initiates a calibration cycle when a variation in magnitudes of at least two most recent samples of the input signal has remained within a first predetermined limit, provided that a predetermined minimum number of clock signal cycles have occurred since the calibration timing circuit last initiated a calibration cycle. The ADC may also refrain from initiating a calibration cycle unless a magnitude of a most recent sample of input signal is within a second predetermined limit.

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Ian Galton., “Digital Cancellation of D/A Converter Noise in Pipeline A/D Converter,”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Proceeding, Mar. 2000. pp. 185-196, vol. 47, No. 3.

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