Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2005-11-22
2005-11-22
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000
Reexamination Certificate
active
06967603
ABSTRACT:
A background calibrating, skip and fill, analog/digital converter (ADC) generates an output data sequence having successive data elements representing magnitudes of successive samples of an analog input signal (X) acquired during successive cycles of a clock signal. The ADC normally samples the analog input signal during most clock cycles, but occasionally executes a calibration cycle in which it samples a reference signal of known magnitude, determines the error in its output data, and calibrates itself to eliminate the error. The ADC calculates a magnitude of data elements of the output sequence corresponding to samples of the input signal that were skipped during a calibration cycle by interpolating preceding and succeeding sample values. The ADC initiates a calibration cycle when a variation in magnitudes of at least two most recent samples of the input signal has remained within a first predetermined limit, provided that a predetermined minimum number of clock signal cycles have occurred since the calibration timing circuit last initiated a calibration cycle. The ADC may also refrain from initiating a calibration cycle unless a magnitude of a most recent sample of input signal is within a second predetermined limit.
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Bedell Daniel J.
Jean-Pierre Peguy
Lauture Joseph
Realtek Semiconductor Corp.
Smith-Hill and Bedell
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