Adaptor circuit for adapting a test facility to a unit under tes

Details Adaptor circuit for adapting a test facility to a unit under tes Adaptor circuit for adapting a test facility to a unit under tes

1983-04-21

1986-08-19

Strecker, Gerard R.

Electricity: measuring and testing

Plural, automatically sequential tests

307265, 307475, 324 73R, 324158R, 364579, G01R 1512

Patent

active

046072144

ABSTRACT:
Test signals emitted by a test facility A may have a chronological offset relative to a defined time point which is unacceptable for certain units under test having a fast response circuitry. A system is inserted between the test facility and such a unit under test so as to provide a smaller chronological offset. This system contains a transmitter and a receiver connected in anti-parallel fashion with respect to one another. The transmitter connects the test signal of the test facility through to the unit under test as a test signal only when a clock signal and a change-over signal are present at the transmitter. The clock signal can be generated at a determinable point in time in a simple manner and thus the point in time of the appearance of the various test signals can be determined without a great offset from this point in time. The receiver is cut in with the assistance of a clock signal and by means of a cut-in signal, and then emits a result signal based on the signal from the unit under test to the test facility. The clock signal for the transmitter and the clock signal for the receiver are both obtained from a given clock signal with the assistance of time-delay means.

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patent: 4399405 (1983-08-01), Welzhofer
patent: 4465971 (1984-08-01), Abeyta

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