Adaptive write-back method and apparatus wherein the cache syste

Details Adaptive write-back method and apparatus wherein the cache syste Adaptive write-back method and apparatus wherein the cache syste

1995-04-10

1995-10-31

Swann, Tod R.

Boots, shoes, and leggings

395469, 395470, 395432, 36424341, 3642543, 364DIG1, 3649571, 364964341, 364964342, 364DIG2, G06F 1200, G06F 1212, G06F 1300

Patent

active

054637597

ABSTRACT:
Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

REFERENCES:
patent: 5301299 (1994-04-01), Pawlowski et al.
patent: 5303364 (1994-04-01), Mayer et al.
patent: 5418927 (1995-05-01), Chang et al.

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