Boots – shoes – and leggings
Patent
1992-05-28
1995-11-21
Rudolph, Rebecca L.
Boots, shoes, and leggings
36424341, 364964342, 364964343, 364DIG1, 364DIG2, 395494, 395469, 395470, G06F 1200, G06F 1300
Patent
active
054695554
ABSTRACT:
Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.
REFERENCES:
patent: 4426682 (1984-01-01), Rife et al.
patent: 4493026 (1985-01-01), Olnowich
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4794523 (1988-12-01), Adan et al.
patent: 4805098 (1989-02-01), Mills, Jr.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4847758 (1989-07-01), Olson et al.
patent: 4920477 (1990-04-01), Colwell et al.
patent: 4953073 (1990-08-01), Moussouris et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 5008813 (1991-04-01), Crane et al.
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5091850 (1992-02-01), Culley
patent: 5095428 (1992-03-01), Walker et al.
patent: 5097532 (1992-03-01), Borup et al.
patent: 5113506 (1992-05-01), Moussouris et al.
patent: 5119485 (1992-06-01), Ledbetter et al.
patent: 5157774 (1992-10-01), Culley
patent: 5182802 (1993-01-01), Dillard
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5249283 (1993-09-01), Boland
patent: 5257360 (1993-10-01), Schnizlein et al.
patent: 5285323 (1994-02-01), Hetherington et al.
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5303362 (1994-04-01), Butts, Jr. et al.
patent: 5303364 (1994-04-01), Mayer et al.
Buchanan, "A Highly Integrated VLSI Chip Set For EISA System Design", Silicon Valley Personal Computer Design Conference Proceedings, Jul. 9-10, 1991, pp. 293-306.
MicroDesign Resources, Inc., "PC Chip Sets" (1992), Chap. 4.
Cypress Semiconductor Corp., CMOS BiCMOS Data Book (Mar. 1, 1991), pp. 2-297 through 2-315 (CY7B180/CY7B181).
Intel Corp., i486.TM. Processor Hardware Reference Manual (1990), pp. 6-1 through 6-11.
Intel Corp., 82350DT Eisa Chip Set (Sep. 1991).
Intel Corp., 82350 EISA Chip Set, Peripheral Components, Data Book (Jul. 1990).
Texas Instruments Corp., TACT84500 EISA Chip Set, Preview Bulletin (1991).
OPTi Inc., OPTi-386WB PC/AT Chipset (82C391/82C392/82C206), Databook, Version 1.2 (Mar. 28, 1991).
OPTi, Inc., HiD/386 AT Chipset High Integration Dilect Mapped Cache AT 82C381/82C382D-25/33, Data Book (Nov. 1989).
OPTi, Inc., OPTi-386/486WB EISA Chipset (82C681/82C682/82C686/82C687), Databook, Version 1.3 (1991).
Bhattacharya Dipankar
Ghosh Subir K.
Asta Frank J.
OPTi Inc.
Rudolph Rebecca L.
LandOfFree
Adaptive write-back method and apparatus wherein the cache syste does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adaptive write-back method and apparatus wherein the cache syste, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive write-back method and apparatus wherein the cache syste will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1145030