Boots – shoes – and leggings
Patent
1995-02-03
1997-01-14
Envall, Jr., Roy N.
Boots, shoes, and leggings
395800, 382250, 382251, G06F 738
Patent
active
055946798
DESCRIPTION:
BRIEF SUMMARY
This application is a 371 of PCT/JP94/00525 Mar. 30, 1994.
TECHNICAL FIELD
The present invention relates to a central processing unit (processing apparatus) in a computer system used for example for calculation of numerical values, image processing, graphic processing, etc., and particularly relates to an adaptive video signal processing apparatus, for example, a digital signal processor (DSP), suitable for video signal processing such as image compression and encoding (CODEC).
BACKGROUND ART
In recent years, a large number of digital signal processors (DSP) for image codex have been proposed based on image compression and encoding/expansion and decoding standards such as the CCITT H. 261 recommendation, MPEG, or the like.
Among these DSP's, the present invention relates to a DSP of a "single instruction stream.multidot.multiple data stream (SIMD)" control system which has a plurality of processing units each comprising an arithmetic and logic unit, multiplier, accumulator, etc., wherein these processing units perform parallel processing on a plurality of data by a single instruction flow, as disclosed in Yamauchi et al, "Architecture and Implementation of a Highly Parallel Single-Chip Video DSP", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 2, NO. 2, JUNE 1992, pp. 207-220.
The configuration disclosed in this reference is shown in FIG. 1. The processing unit of this DSP can connect processors in a pipeline and also performs pipeline processing of computations.
A simple explanation will be made first of a principle of the computation pipeline.
FIG. 2 shows an example of the configuration of the computation pipeline. This computation pipeline is one in which two inputs X and Y are added at an arithmetic and logic unit (ALU) A1, the result of addition and the coefficient from a coefficient memory A3 are multiplied at a multiplier A2, and the result of that multiplication is then accumulated at an accumulator A3. Continuous performance of a chain of such computations with respect to a plurality of data is called "computation pipeline processing".
FIG. 3 is a graph showing a timing chart of the processing in the computation pipeline of FIG. 2. For simplification, it is assumed that the processors A1, A2, and A4 of the computation pipeline complete the computation in one clock cycle.
The "unit of processing" in FIG. 3 means a set (X, Y) of the data input to a two-input terminal.
As shown in FIG. 3, when looking for example at the i-th unit of processing, processing; processing. Also, when looking at the k-th clock cycle, multiplication processing is accumulated at the accumulator A4, multiplier A2, and
By repeatedly performing such an operation with respect to a plurality of units of processing, the computation pipeline processing can be realized.
Next, an explanation will be made of a prior art.
Here, a DSP of the "single instruction stream.multidot.multiple data stream (SIMD)" control system which has been proposed in the above-mentioned reference, in which four sets of processing units perform parallel processing on a plurality of data by a single instruction flow will be considered.
As a prerequisite, it is assumed that each processing unit is comprised of three types of processors, that is, an arithmetic and logic unit (ALU) performing the addition, subtraction, and the logical computation, a multiplier, and an accumulator. Also, for ease of the explanation, it is assumed that each processor completes the computation in one clock cycle. Accordingly, this DSP can execute 12 computations (for example, four addition, four multiplication, and four accumulation operations) at the maximum in one clock cycle. Further, it is assumed that this DSP has a data memory for supplying the data to the processors or storing the data from the processors inside a chip or outside the chip.
First, the configuration for realizing the computation pipeline having the highest degree of freedom will be explained based on the above-described prerequisites.
As shown in FIGS. 4A to 4D, the computation pip
REFERENCES:
patent: 5179531 (1993-01-01), Yamaki
patent: 5260897 (1993-11-01), Toriumi et al.
patent: 5299319 (1994-03-01), Vassiliadis et al.
Yamauchi et al. "Architecture and Implementation of a Highly Parallel Single-Chip Video DSP", IEEE Transactions on Circuits and Systems for Video Technology, vol. 2, No. 2, Jun. 1992, pp. 207-220.
Envall Jr. Roy N.
Kananen Ronald P.
Moise Emmanuel L.
Sony Corporation
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