Adaptive timing using clock recovery

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Details

C375S375000

Reexamination Certificate

active

08077807

ABSTRACT:
Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.

REFERENCES:
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patent: 6397042 (2002-05-01), Prentice et al.
patent: 7012972 (2006-03-01), Isaksen et al.
patent: 7349506 (2008-03-01), Shizuki
patent: 7363563 (2008-04-01), Hissen et al.
patent: 2003/0123589 (2003-07-01), Glenn et al.
patent: 2004/0213337 (2004-10-01), Li et al.
patent: 2005/0286669 (2005-12-01), Buchwald et al.

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