Adaptive test time reduction for wafer-level testing

Details Adaptive test time reduction for wafer-level testing Adaptive test time reduction for wafer-level testing

2007-09-05

2009-12-01

Nguyen, Ha Tran T (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07626412

ABSTRACT:
A method is provided for dynamically increasing or decreasing the amount of test data that is applied to die locations on a wafer under test. As on-wafer locations are traversed and tested, the amount of test stimuli applied to subsequent locations is adjusted. This adjustment is based upon the results of previously tested locations. The effect is that the test program detects regions of the wafer that are more likely to fail and applies more complete testing to these areas. Other areas of the wafer may receive reduced testing. By automatically adapting the test mix to suit the potential failure patterns, wafer testing time is reduced.

REFERENCES:
patent: 6853206 (2005-02-01), Hubner et al.
patent: 7165004 (2007-01-01), Dorough et al.

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