Adaptive test time reduction for wafer-level testing

Details Adaptive test time reduction for wafer-level testing Adaptive test time reduction for wafer-level testing

2011-01-04

2011-01-04

Nguyen, Ha Tran T (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07863923

ABSTRACT:
In a method for testing a plurality of consecutively indexed sites, a default test sequence is applied to the consecutively indexed sites until a first defective site is identified. If a first defective site is identified, then a more stringent test sequence is applied to a predefined number of sites subsequent to the first defective site. If the more stringent test sequence does not identify a second defective site in the predefined number of sites subsequent to the first defective site, then the default test sequence is resumed.

REFERENCES:
patent: 6853206 (2005-02-01), Hubner et al.
patent: 7165004 (2007-01-01), Dorough et al.

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