Adaptive sweep bit synchronizer

Pulse or digital communications – Spread spectrum – Direct sequence

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307511, 307527, 328 63, 331 4, H03L 706

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active

043756930

ABSTRACT:
A partly analog partly digital bit synchronizer capable of acquisition and operation over an arbitrarily broad range of data rates is disclosed. A second order phase lock loop (PLL) is employed providing both phase and frequency correction to a voltage controlled oscillator (VCO). The phase detector consists of a binary counter whose most significant bit (MSB) is defined to be the recovered clock. The desired data transition points are defined as coinciding with the falling edge of the counter's MSB. At each data transition, the least significant bits within the counter are used to set the duration of phase and frequency correction pulses proportional to the phase error, which pulses are then fed to the VCO. An acquisition circuit diverts the frequency correction pulses in order to sweep the VCO within a selected half octave. Lock is recognized when a preselected number of data transitions with phase error below a preset maximum occur consecutively. An autorange capability automatically steps the frequency through half octaves within an arbitrarily large range.

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Bellisio, J. A., "A New Phase Locked Timing Recovery Method for Digital Regenerators", IEEE, International Conference on Communications, Jun. 1976, Philadelphia, Pa., pp. 10-17 et seq.

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