Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2003-02-04
2004-04-27
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S076000, C341S077000, C341S155000, C375S242000, C375S244000, C375S247000
Reexamination Certificate
active
06727833
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to signal processing, and more particularly, to analog to digital conversion using sigma-delta modulation.
BACKGROUND ART
Sigma-delta (&Sgr;-&Dgr;) modulation is a widely used and thoroughly investigated technique for converting an analog signal into a high-frequency digital sequence. See, for example, “Oversampling Delta-Sigma Data Converters,” eds. J. C. Candy and G. C. Temes, IEEE Press, 1992, and “Delta-Sigma Data Converters,” eds. S. R. Northworthy, R. Schreier, G. C. Temes, IEEE Press, 1997, both of which are hereby incorporated herein by reference.
In &Sgr;-&Dgr; modulation, a low-resolution quantizer is incorporated within a feedback loop configuration in which the sampling frequency is much higher than the Nyquist frequency of the input signal (i.e., much higher than twice the maximum input frequency). In addition, the noise energy introduced in the quantizer is shaped towards higher frequencies according to a so called “noise transfer-function” NTF(z), and the signal passes the modulator more or less unchanged according to a so called “signal-transfer-function” STF(z).
FIG.
1
(
a
) depicts a simple first order &Sgr;-&Dgr; modulator for a discrete time system having a subtraction stage
101
, an accumulator
102
(including an integrator adder
103
and a delay line
104
), and a one-bit quantizer
105
. In normal operation, an input signal x(n) within the range [−a≦x(n)≦a] is converted to the binary output sequence y
a
(n)&egr;±a. The quantizer
105
produces a+1 for a positive input and a −1 for a negative input. The output from the quantizer
105
is fedback and subtracted from the input signal x(n) by the subtraction stage
101
. Thus, the output of the subtraction stage
101
will represent the difference between the input signal x(n) and the quantizer output signal y
a
(n). As can be seen from FIG.
1
(
a
), the output of the accumulator
102
represents the sum of its previous input and its previous output. Thus, depending on whether the output of the accumulator
102
is positive or negative, the one-bit quantizer
105
outputs a+1 or a −1 as appropriate.
As can be seen in FIG.
1
(
b
), if the quantizer
105
is replaced by an adder
106
and a noise source
107
the basic relationship between the z-transforms of system input x(n), quantizer noise &ggr;
a
(n); and the two-level output sequence y(n) is:
Y
a
(
z
)=
z
−1
X
(
z
)+(1−
z
−1
)&Ggr;
a
(
z
),
where index “a” denotes the amplitude of sequence y
a
(n), i.e., y
a
(n) &egr;±a. The signal transfer function and noise transfer function can be identified as STF(z)=z
−1
and NTF(z)=(1−z
−1
), respectively.
For higher order modulators, the signal transfer unction remains unchanged, and the noise transfer function becomes NTF(z)=(1−z
−1
)
k
, where k denotes the order of the modulator. The signal-transfer function STF(z)=z
−1
means that the input signal is represented in the output sequence y
a
(n), delayed by one sampling clock period. This transfer function does not contain any bandwidth limitations of the input signal. Any input signal x(n) within the range [−a+a] can be processed by the &Sgr;-&Dgr; modulator, including discontinuous signals with step-like transitions. For the modulator depicted in
FIG. 1
, this can easily be demonstrated, if it is regarded as a linear (non-adaptive) delta modulator, whose input is the accumulated input x(n). If the input is within the range [−a≦x(n)≦a], the magnitude of the maximum slope of the accumulated sequence x(n) is a a/T (with T as sampling period). Thus, the delta modulator can always track its input, and so called “slope-overload conditions” cannot occur.
In most applications, this basic &Sgr;-&Dgr; feature is not exploited. In order to cut off the shaped out-of-band-quantization noise, the &Sgr;-&Dgr; output sequence y
a
(n) is low-pass filtered (usually by means of linear filters), thereby removing also the spectral components of x(n) outside the base band.
SUMMARY OF THE INVENTION
An adaptive sigma delta modulator is provided. The adaptive sigma delta modulator includes an input stage, a sigma delta modulator, an adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal in a first amplitude range and an adaptive feedback signal. The sigma delta modulator produces an intermediate digital output sequence in a reduced second amplitude range representative of the difference signal. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the reduced second range. The output stage produces a final digital output sequence which is the sum of the intermediate digital output sequence and a delayed adaptive feedback signal. The final digital output sequence has an amplitude in the first range and is a digital representation of the analog input. In one embodiment, the adaptive feedback signal is delayed by one clock period. The adaptive feedback signal may include an estimate of the instantaneous input signal and the sign of a quantizer output signal multiplied by an amplitude smaller than the amplitude of the input signal. In a preferred embodiment, the sigma delta modulator is of the first order.
In a further embodiment, an adaptive sigma delta modulator is provided wherein the input stage includes a plurality of capacitors connected in parallel and a switch control logic device for charging and discharging the capacitors.
A method for adapting sigma delta modulation is also provided. A difference signal representing the difference between an analog input signal in a first amplitude range and an adaptive feedback signal is produced. An intermediate digital signal output sequence in a reduced second amplitude range representative of the difference signal is also produced. The adaptive feedback signal is produced and the amplitude of the adaptive feedback signal keeps the difference signal within the reduced second range. Lastly, a final digital output sequence is produced. The final digital output sequence is the sum of the intermediate digital output sequence and a delayed adaptive feedback signal representative of the adaptive feedback signal. The final digital output sequence has an amplitude in the first range.
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Delta-Sigma Data Converters: Theory, Design and Simulation; Edited by Norsworthy, et al., IEEE Press, New York, NY 1997.
Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation; Edited by Candy, et al.; IEEE Press, New York, NY 1992.
Bromberg & Sunstein LLP
MED-EL Elektromedizinische Geraete GmbH
Nguyen K
Tokar Michael
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