Adaptive scalable cache coherence network for a multiprocessor d

Details Adaptive scalable cache coherence network for a multiprocessor d Adaptive scalable cache coherence network for a multiprocessor d

1996-11-13

1998-07-14

Swann, Tod R.

39520002, 39520003, 3952001, 39520016, 39520015, 39520021, 395297, 395300, 395446, 395447, 395448, 395468, 395449, 395471, 395472, 395473, 395730, 395731, 395800, G06F 1300

Patent

active

057817570

ABSTRACT:
A cache coherence network for transferring coherence messages between processor caches in a multiprocessor data processing system is provided. The network includes a plurality of processor caches associated with a plurality of processors, and a binary logic tree circuit which can separately adapt each branch of the tree from a broadcast configuration during low levels of coherence traffic to a ring configuration during high levels of coherence traffic. A cache snoop-in input receives coherence messages and a snoop-out output outputs, at the most, one coherence message per current cycle of the network timing. A forward signal on a forward output indicates that the associated cache is outputting a message on snoop-out during the current cycle. A cache outputs received messages in a queue on the snoop-out output, after determining any response message based on the received message. The binary logic tree circuit has a plurality of binary nodes connected in a binary tree structure. Each branch node has a snoop-in, a snoop-out, and a forward connected to each of a next higher level node and two lower level nodes. A forward signal on a forward output indicates that the associated node is outputting a message on snoop-out to the higher node during the current cycle. Each branch ends with multiple connections to a cache at the cache's snoop-in input, snoop-out output, and forward output.

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