Adaptive or fault tolerant full wafer nonvolatile memory

Details Adaptive or fault tolerant full wafer nonvolatile memory Adaptive or fault tolerant full wafer nonvolatile memory

1989-12-29

1992-04-14

Atkinson, Charles E.

Excavating

365200, 365201, G01R 3128

Patent

active

051054256

ABSTRACT:
A method and apparatus for providing a flexible and adaptive communication link from one of four wafer input/output channels respectively located on each of four sides of a silicon wafer to a predetermined internal memory-logic site includes in a matrix array of indentical memory-logic sites located on the wafer. A new linkage path can be formed, if necessary, each time a memory-logic is accessed. Each memory-logic site is capable of communicating with any of its neighboring sites, which includes not only its four opposing sides, but also its four adjacent diagonal sites, by one of a plurality of input/output site ports. A programmed external controller coupled to a computer, for example, works from the edge of the wafer through the selected wafer input/output channel and links to any designated memory-logic site for the purpose of data storage, data retrieval or test.

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