Amplifiers – With periodic switching input-output
Reexamination Certificate
1999-04-13
2001-02-27
Pascal, Robert (Department: 2817)
Amplifiers
With periodic switching input-output
C330S253000
Reexamination Certificate
active
06194962
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of operational amplifier offset voltage (V
os
) trimming techniques, and particularly to V
os
trimming for op amps with rail-to-rail input stages.
2. Description of the Related Art
“Input offset voltage” (V
os
) is a parameter associated with operational amplifiers (op amps), defined as the output voltage produced by the op amp when its differential input voltage is zero. An untrimmed V
os
can be on the order of millivolts, which appears as an error in the amplifier's output. When a highly accurate op amp is needed, a trimming method is typically used to make V
os
as small as possible; such methods include laser trimming a resistor during assembly, and applying a fixed “trim current” to a particular circuit node.
Rail-to-rail op amps, i.e., op amps which function for input signals that vary up to the amplifier's positive and negative supply voltages, pose an especially troublesome trimming problem. This is because such op amps typically employ complementary differential pairs, instead of the single differential pair found in conventional amplifiers. Each of the two differential pairs has a respective offset voltage, with the degree to which the amplifier's output is affected by the offset voltages being dependent on which of the pairs is conducting at any given time.
A conventional rail-to-rail op amp is shown in FIG.
1
. The gates of a first differential pair of transistors M
1
and M
2
are connected across the amplifier's differential input terminals V
in+
and V
in−
; M
1
and M
2
are biased with a current source I
1
connected between their respective sources and a negative supply voltage V
SS
. A second pair of transistors M
3
and M
4
are also connected across V
in+
and V
in−
, and are biased with a current source I
2
connected between their respective sources and positive supply voltage V
DD
. Each pair produces a respective differential output current between its two drain terminals. All four drain terminals are connected to an output stage
10
, which converts the differential output currents to a single ended output current I
OUT
.
In the circuit shown in
FIG. 1
, M
1
and M
2
are n-channel FETs having their sources referenced to V
SS
, and M
3
and M
4
are p-channel FETs having their sources referenced to V
SS
, enabling the amplifier to handle rail-to-rail input voltages. Both pairs of transistors are active at the same time, except when the input common-mode voltage (V
cm
) is close to either rail. One of the pairs turns off when this occurs, because its transistors' gate-to-source voltages (V
gs
) become less than their threshold voltages (V
T
). Thus, only M
1
and M
2
are active if V
cm
is above about V
DD
−1 volt, and only M
3
and M
4
are active if V
cm
is below about V
SS
+1 volt.
As noted above, both differential pairs contribute to the amplifier's offset voltage. V
os
is fairly constant over that portion of the common-mode input range for which both pairs are active, and this V
os
value can be reduced by trimming. Unfortunately, V
os
will change when one or the other of the pairs stop conducting near the supply rail. When this occurs, the trim adjustment made to correct V
os
when both pairs are active is now incorrect, and V
os
will increase.
Another known rail-to-rail op amp is disclosed in U.S. Pat. No. 5,610,557 to Jett, Jr., and is shown in FIG.
2
. Two complementary differential pairs
20
and
22
are connected across the amplifier's differential input terminals V
in+
and V
in−
. A constant current source I
3
biases differential pair
22
, and a constant current source
24
biases differential pair
20
. A transistor Q
steer
is connected between I
3
and current source
24
, and receives a reference voltage V
ref
at its base. When Q
steer
is not conducting, pair
22
receives bias current I
3
and is active. When Q
steer
begins to conduct, at a common-mode input voltage established by the value of V
ref
, I
3
is diverted to current source
24
, disabling pair
22
and activating pair
20
. Thus, only one pair is active at a time over most of the amplifier's common-mode input range.
The collector currents of the two pairs are connected to an output stage
26
, which converts the two differential currents to a single-ended output current I
out
. A V
os
trimming capability is provided by four variable resistors R
1
-R
4
in output stage
26
. R
1
and R
2
are adjusted to trim V
os
when pair
20
is active, and R
3
and R
4
trim V
os
when pair
22
is active. There are several drawbacks to this trimming approach, however. The trim currents provided by R
1
-R
4
are always present regardless of which differential pair is active, and while a pair's respective trim currents may be appropriate when its pair is active, they are unlikely to be ideal when the other pair is active. Furthermore, R
1
/R
2
and R
3
/R
4
are adjusted when their respective pairs are fully conducting. However, there is a transition region over which one pair stops conducting while the other pair starts conducting. Because the fixed trim currents provided by R
1
-R
4
are adjusted to correct V
os
for common-mode voltages on either side of the transition region, the amplifier's V
os
—and the inaccuracy of I
out
—increases for common-mode input voltages that fall within the transition region.
SUMMARY OF THE INVENTION
A system for adaptively trimming the input offset voltage of an op amp is presented which overcomes the problems noted above. The invention provides accurate V
os
trimming over an amplifier's entire common-mode input range, by providing an “adaptive” trim signal that varies with the current conducted by the amplifier's input stage.
The system is used with an op amp having complementary differential pairs in its input stage, which are typically provided to give the op amp a rail-to-rail common-mode input voltage range. Switching circuitry insures that only one pair is active at a time, except in a transition region in which both pairs are partially conducting. The op amp's output stage includes a trim input by which the amplifier's output can be adjusted to reduce V
os
. Trim circuitry is employed which tracks the current in at least one of the pairs, and generates an “adaptive” trim signal which varies with the tracked current. This adaptiveness enables V
os
to be kept low over the full range of common-mode input voltages, including in the amplifier's transition region.
In a preferred embodiment, the switching circuitry controls which pair is active by forcing the first pair to turn off while providing bias current to activate the second pair. The trim circuitry preferably provides two outputs to the output stage's trim input: one trim signal which is constant with respect to common-mode input voltage, and an adaptive trim signal which varies with the bias current fed to the second pair. The generation of an adaptive trim signal enables V
os
to be reduced even for common-mode input voltages in the transition region.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
REFERENCES:
patent: 4766394 (1988-08-01), Yukawa
patent: 4797631 (1989-01-01), Hsu et al.
patent: 4887048 (1989-12-01), Krenik et al.
patent: 5293136 (1994-03-01), Ryat
patent: 5610557 (1997-03-01), Jett, Jr.
patent: 5734297 (1998-03-01), Huijsing et al.
patent: 5764101 (1998-06-01), Archer
Analog Devices Inc.
Choe Henry
Koppel & Jacobs
Pascal Robert
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