Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1998-06-26
2001-06-19
Hafiz, Tariq R. (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
Reexamination Certificate
active
06249906
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention relates generally to monitoring the performance of a computer processing system for improvement in its operation. More particularly, the present invention relates to monitoring the performance of the operation of a computer processing system when executing an application program by profiling the instances of operational segments of the program such as long table walks and cache misses, analyzing the profiled data, and modifying the object code in order to improve the operation of the application program in the processing system.
BACKGROUND OF THE INVENTION
Profiling the execution of an application program in computer processing systems has shown that it may take a long time to execute certain segments of the program. These delays are often caused by long table walks or long cache misses. This is often the result of writing the application program in a high level language that can be easily ported to different platform configurations. Also, tuning the application program to run efficiently on a specific platform configuration is usually given lower priority than providing new functions in the application program. As a result, tuning an application program to run more efficiently on a specific platform configuration is performed for only a few applications.
There are several approaches that have been developed to optimize or tune object code to run more efficiently on a specific platform configuration. One approach is described in U.S. Pat. No. 5,452,457. Under this approach, compiler directives are inserted in the source code, the source code is compiled, and the resultant object code is performance tested and data is accumulated. Based on the accumulated data, the compiler directives are modified and the source code is recompiled. Another approach is to profile an application program to identify the critical blocks in the code, and to hand tune the code to minimize the effects of critical blocks such as long table walks or long cache misses. All of the known approaches to optimizing can require a significant amount of off-line operator interaction and analysis. Because of the complexity of the issues involved, application program optimization is not usually performed by the end user. Other patents relating to performance monitoring include U.S. Pat. Nos. 5,727,167 and 5,748,855.
Therefore, there is a need for an automated method of optimizing application programs on a specific platform configuration that minimizes the effects of long table walks and long cache misses. It is desirable that this optimization can be performed by the end user as the need arises.
SUMMARY OF THE INVENTION
The present invention provides an automated method of optimizing application programs on a specific hardware platform configuration that minimizes the effects of long table walks and long cache misses, while enabling the end user to perform this optimization when needed. In accordance with one aspect of the present invention, the platform configurations to be optimized include a performance monitoring capability. This performance monitoring capability is a software accessible mechanism for providing detailed information concerning the utilization of the processor instruction execution and memory management operation. The performance monitor, as found on the PowerPC manufactured by IBM Corporation, consists of an implementation dependent number of 32 bit counters for counting processor and memory management related events. The number of performance monitor counters may vary, but is typically between two and eight 32 bit counters (PMC
0
, PMC
1
, . . . , PMC
7
). The performance monitor counters are controlled by two monitor mode control registers (MMCRO, MMCR
1
) that establish the function of the counters. The performance monitor counters and the monitor mode control registers are addressable for read and write instructions. The monitor mode control registers are partitioned into bit fields that allow for selection of events to be recorded or counted. Selection of allowable combination of events causes the counters to operate concurrently. The monitor mode control registers may include bit fields for enabling the counters, controlling interrupts, selecting the event to be counted, and for freezing counter control. The number of events that can be selected for counting is implementation dependent. Other registers that may be used to support the performance monitor are the sampled instruction address register (SIAR) and the sampled data address register (SDAR). The SIAR stores the effective address of an instruction being sampled while the SDAR stores the effective address of the operand of the instruction whose effective address is stored in the SIAR.
The present invention uses the performance monitoring capability to optimize an application program by (1) profiling the program to identify the effective addresses in segments of object code that result in long table walks or long cache misses; (2) analyzing the results of the profiling operation to determine where to insert instructions into the object code that minimizes delays caused by long table walks or long cache misses; and (3) inserting instructions into the object code that minimize the effects of long table walks and long cache misses by preloading or “touching” an instruction or data. The optimizing program may make changes to the object code in real time or may save the program changes in an optimized change file. This change file may be stored on the local machine for direct updating, may be stored on a server for downloading to specific processors, or may be provided to a linker/loader program for optimizing during the compilation process.
In an embodiment of the present invention, an adaptive method for minimizing the effect of long table walks in a processing system comprises initializing a performance monitor for monitoring table walks, profiling an application program by using the performance monitor to collect table walk data, building effective address tables from the table walk data to associate effective addresses of offending instructions that create long table walks with the table walks of long duration, optimizing the application program by determining where to position preload instructions in an instruction sequence of the application program object code prior to effective address positions of the offending instructions that create long table walks, building an optimized change file from the determination of the positions of the preload instructions in the instruction sequence, applying the optimized change file to the object code of the application program, testing the optimized object code for minimized long table walks, and repeating the previous steps if long table walks are not minimized. The step of initializing a performance monitor for monitoring table walks may comprise setting bit configurations in control fields in a primary monitor mode control register for controlling a first performance monitor counter and a thresholder. Alternatively, the step of initializing a performance monitor for monitoring table walks may comprise setting bit configurations in control fields in a primary monitor mode control register and a secondary monitor mode control register for controlling a plurality of performance monitor counters and a thresholder. The step of profiling an application program by using the performance monitor to collect table walk data may comprise counting a predetermined number of table walks that exceed a threshold time interval value in a first performance monitor counter, signaling an interrupt when a most significant bit in the first performance monitor counter transitions from a logical 0 to a logical 1, loading an effective address of an executing instruction into a sampled instruction address register when the interrupt is signaled, and loading an effective address of an operand of the executing instruction into a sampled data address register when the interrupt is signaled. The step of profiling an application program by using the performance monitor to
Levine Frank Eliot
Roth Charles Philip
Das Chameli Chaudhuri
England Anthony
Hafiz Tariq R.
International Business Machines Corp.
Taylor Russell & Russell P.C.
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