Adaptive method and apparatus to control loop bandwidth of a...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

Reexamination Certificate

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C331S025000

Reexamination Certificate

active

06980060

ABSTRACT:
Disclosed is a PLL (Phase Lock Loop) reducing the lock-in-time of the phase lock loop by altering the impedance of the damping resistor portion of the included LPF (Low Pass Filter) as a function of the difference in frequency or phase between a PLL applied reference frequency and the output frequency provided by the VCO (Voltage Controlled Oscillator) portion of the PLL. This variable impedance is accomplished by introducing a feed forward path that switches a capacitor in and out of the circuit in accordance with the difference frequency. One embodiment uses a mixer to provide the difference frequency signal.

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Fahim, A.M. and Elmasry, M.I.; “A Fast Lock Digital Phase-Locked-Loop Architecture for Wireless Applications”;IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing; Feb. 2003; vol. 50, No. 2; pp. 63-72.
Lee, Joonsuk and Kim, Beomsup; “A Low Noise Fast Lock Phase Locked Loop With Adaptive Bandwidth Control”;IEEE Journal of Solid-State Circuits; Aug. 2000; vol. 35, No. 8; pp. 1137-1145.
Roh, Gyoung-Tae, Lee, Yong Hoon and Kim, Beomsup; “Optimum Phase Acquisition Technique for Charge Pump PLL,”IEEE Transactions on Circuits and System-II: Analog and Digital Signal Processing; Sep. 1997; vol. 44, No. 9; pp. 729-740.

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