Adaptive loop bandwidth circuit for a PLL

Details Adaptive loop bandwidth circuit for a PLL Adaptive loop bandwidth circuit for a PLL

2005-06-21

2005-06-21

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S011000, C331S017000, C331S025000, C327S012000, C327S157000, C327S159000

Reexamination Certificate

active

06909329

ABSTRACT:
A phase-locked loop (PLL) employs a phase detector (PD) generating an up/down signal based on the phase error between a data signal and a clock signal input to the phase detector. The PD senses excess jitter and extends the loop bandwidth to accommodate such excess jitter. Phase error is derived by sampling of the clock signal and at least one phase-shifted version of the clock signal by the data signal, and a retimed data is generated by the PD by sampling of the data signal by the clock signal. The sampled clocks are employed to generate a modified control signal with greater resolution in detecting the phase error, which, in turn, increases the loop bandwidth.

REFERENCES:
patent: 5301196 (1994-04-01), Ewen et al.
patent: 6041090 (2000-03-01), Chen
Joseph Adler, “Clock-source jitter: A clear understanding aids oscillator selection”; EDN, Feb. 18, 1999, pps. 79-86.

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