Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-12-07
2001-03-06
Nguyen, Matthew (Department: 2838)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
Reexamination Certificate
active
06198330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to inverters and, more particularly, to complementary metal-oxide semiconductor inverters.
2. Description of the Related Art
FIG. 1
illustrates a conventional inverter
20
that is realized with complementary metal-oxide semiconductor (CMOS) devices. The inverter has a complementary common-source stage
22
coupled between a single-ended input port
24
and a single-ended output port
26
. In more detail, the complementary common-source stage
22
includes a P-channel metal-oxide semiconductor (PMOS) transistor
28
and an N-channel metal-oxide semiconductor (NMOS) transistor
30
. The transistors
28
and
30
have their gates coupled to the input port
24
, their drains coupled to the output port
26
and their sources respectively coupled to a supply voltage V
DD
and a ground
32
.
Various references on CMOS transistors (e.g., Gray, Paul R., et al,
Analysis and Design of Analog Integrated Circuits,
John Wiley and Sons, New York, 1993, p. 59-66), explain that a conductive channel exists between a drain and a source when a gate-to-source voltage V
GS
is greater than the threshold voltage V
T
and, accordingly, a drain-to-source voltage V
DS
will cause current to flow between the drain and source. When V
DS
is less than V
GS
−V
T
, the transistor is said to be in its triode region in which the drain current is given by
I
D
=
K
′
2
W
L
{
2
(
V
GS
-
V
T
)
V
DS
-
V
DS
2
}
(
1
)
wherein K′ is the product of the channel's average electron mobility and the gate oxide capacitance per unit area and W and L are respectively the channel's width and length. In this triode region, a CMOS transistor behaves as a nonlinear voltage-controlled resistor. When V
DS
is greater than V
GS
−V
T
, the transistor is said to be in its saturation region in which the drain current is given by
I
D
=
K
′
2
W
L
(
V
GS
-
V
T
)
2
(
2
)
and the transistor behaves as a voltage-controlled current source. When V
GS
is less than the threshold voltage V
T
, a drain-to-source voltage V
DS
will not cause current to flow between the drain and source and the transistor is said to be in cutoff.
Because of this transistor behavior, the inverter
20
will generate a transfer curve
38
that is shown in the graph
40
of
FIG. 2
in which V
DD
is approximately 3 volts. When the input signal (at the input port
24
of
FIG. 1
) is low in a first transfer-curve region
42
, transistors
28
and
30
are respectively in the triode region and in cutoff so that the output signal is approximately equal to the supply voltage V
DD
. An increase of input voltage places transistors
28
and
30
respectively in the triode region and in the saturation region so that a voltage drop builds across transistor
28
and the output signal begins to decrease in a transfer-curve region
44
.
This behavior is reversed when the input signal is initially V
DD
, forming a transfer-curve region
46
, and when the input decreases from V
DD
, forming a transfer-curve region
48
. In the transfer-curve region
46
, the transistors
28
and
30
are respectively in cutoff and in the triode region so that the output signal is substantially zero. In the transfer-curve region
48
, the transistors
28
and
30
are respectively in the saturation region and in the triode region and thus a voltage drop builds across transistor
30
and the output signal begins to increase.
When the input signal is in a transfer-curve region
50
that is between transfer-curve regions
44
and
48
, both transistors
28
and
30
are in their saturation region and the output signal transitions between the output signals of these two latter regions.
FIGS. 3A and 3B
show graphs
60
and
62
that respectively illustrate gain and output impedance plots
61
and
63
of the inverter
20
of FIG.
1
. These plots are developed with the aid of small signal models of the transistors
28
and
30
that correspond to transfer-curve regions of FIG.
2
. As recited above, transistors
28
and
30
are respectively in the triode region and in cutoff when the input signal is low and these functions are respectively indicated by a voltage-controlled resistance
71
and an open circuit
72
in the small signal model
64
in
FIGS. 3A and 3B
. When the input signal is near V
DD
, the transistors
28
and
30
are respectively in in cutoff and in the triode region as indicated by the small signal model
65
in
FIGS. 3A and 3B
.
The small signal model
66
demonstrates that the transistors
28
and
30
are respectively in the triode region and in the saturation region (indicated by voltage-controlled current source
73
) as the input signal increases from zero. Conversely, the small signal model
67
demonstrates that the transistors
28
and
30
are respectively in the saturation region and the triode region as the input signal decreases from V
DD
. Finally, the small signal model
68
indicates that the transistors
28
and
30
are both in their saturation region when the input signal is in the transfer-curve region
50
of FIG.
2
.
The small signal models
64
and
65
of
FIGS. 3A and 3B
indicate that the output port (
26
in
FIG. 1
) is respectively connected to V
DD
and to ground with a voltage-controlled resistor so that gain and output impedance are both low in plot portions of
FIGS. 3A and 3B
that respectively correspond to transfer-curve regions
42
and
46
of FIG.
2
. Application arrows
74
and
75
point to the portions of the plots
61
and
63
to which the small signal models
64
and
65
respectively apply.
Voltage-controlled current sources that are coupled to ground and to V
DD
drive the output port in the small signal model
68
of
FIGS. 3A and 3B
. Accordingly, gain and output impedance are high in the plot portions of these figures that correspond to the transfer-curve region
50
of FIG.
2
.
The small signal model
66
of
FIGS. 3A and 3B
couples the output port through a voltage-controlled resistor to V
DD
and through a voltage-controlled current source to ground. Conversely, the small signal model
67
couples the output port through a voltage-controlled current source to V
DD
and through a voltage-controlled resistor to ground. Accordingly, the gain and output impedance in the portions of plots
61
and
63
that correspond to transfer-curve regions
44
and
48
of
FIG. 2
are both lower than in the portions of plots
61
and
63
that correspond to the transfer-curve region
50
.
The plots
61
and
63
of
FIGS. 3A and 3B
demonstrate that gain and output impedance of the inverter
20
of
FIG. 1
significantly vary with changes in input signal. These variations are characteristic of a variable current-drive device and indicate a limited ability to drive inverter loads having different impedances (in particular, low-impedance loads).
SUMMARY OF THE INVENTION
The invention is directed to improved inverters. In particular, it is directed to inverters that can adapt to loads of various impedances to thereby reduce parameter variations and enhance performance of conventional inverters.
In an adaptive-load inverter embodiment, these goals are realized with a complementary common-source stage arranged to drive an output port in response to signals at a first side of a differential input port and a complementary common-drain stage arranged to drive the output port in response to signals at a second side of the differential input port.
The complementary common-source stage functions as an inverter that responds to an input signal and the complementary common-drain stage functions as source followers that are driven by an inversion of the input signal. This structure adapts its output impedance to the driven load and enhances inverter performance (e.g., current drive, switching speed and common-mode rejection).
In another adaptive-load inverter embodiment, a complementary common-source stage is arranged to drive an output port in response to signals at a first side of a diff
Analog Devices Inc.
Koppel & Jacobs
Nguyen Matthew
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