Adaptive lithography in a high density interconnect structure wh

Details Adaptive lithography in a high density interconnect structure wh Adaptive lithography in a high density interconnect structure wh

1990-06-29

1994-10-18

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

174255, 257724, 361792, 361795, H05K 111

Patent

active

053574036

ABSTRACT:
Mispositioning of chips in a high density interconnect structure is compensated for by including a layer having alignment conductor in the high density interconnect structure without requiring adaptation of the signal conductor metallization levels of the high density interconnect structure. One level, two levels or more of alignment conductor may be employed. The alignment levels of the high density interconnect structure are preferably a ground plane, and if two layers of alignment conductors are provided, a power plane.

REFERENCES:
patent: 3705332 (1972-12-01), Parks
patent: 4349862 (1982-09-01), Bajorek et al.
patent: 4628406 (1986-12-01), Smith et al.
patent: 4641425 (1987-02-01), Dubuisson et al.
patent: 4665468 (1987-05-01), Dohya
patent: 4874721 (1989-10-01), Kimura et al.
patent: 4954878 (1990-09-01), Fox et al.
IBM Disclosure Bulletin "Photo--Defined Lamination For Chip Bonding" by J. C. Edwards vol. 25 No. 4 Sep. 1982.
IBM Disclosure Bulletin "Low Inductance Decoupling Capacitor Connection" vol. 28 No. 7 Dec. 1985.

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