Adaptive lithography accommodation of tolerances in chip positio

Details Adaptive lithography accommodation of tolerances in chip positio Adaptive lithography accommodation of tolerances in chip positio

1989-06-05

1991-05-28

Lall, Parshotam S.

Boots, shoes, and leggings

357 75, 364491, G06F 1560

Patent

active

050199978

ABSTRACT:
An adaptive lithography technique for use in high density interconnect circuits compensates for displacements of chip contact pads from their ideal location by including chip contact islands in the metallization pattern and positions a via hole connecting the chip contact island to the chip contact pad where it connects to both of them. The result is simplified routing and avoidance of modifications within the metallization pattern itself to accommodate actual chip placements.

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patent: 4613941 (1986-09-01), Smith et al.
patent: 4743489 (1988-05-01), Hasegawa
patent: 4866508 (1989-09-01), Eichelberger et al.
patent: 4901136 (1990-02-01), Neugebauer et al.
patent: 4930002 (1990-05-01), Takenaka et al.

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