Adaptive integrated PLL loop filter

Details Adaptive integrated PLL loop filter Adaptive integrated PLL loop filter

1999-12-28

2003-04-08

Chin, Stephen (Department: 2734)

Pulse or digital communications

Multilevel

Synchronized

C375S327000, C375S376000, C327S148000, C327S157000, C327S554000, C327S561000, C331S03600C

Reexamination Certificate

active

06546059

ABSTRACT:

BACKGROUND
This disclosure relates to phase-locked loops and more specifically, to a loop filter used in a phase-locked loop.
A phase-locked loop (PLL) is often used in designing a precise clock for a system. The PLL takes advantage of negative feedback to constantly adjust the frequency and phase of an oscillator that may change or drift.
FIG. 1
is a simplified block diagram of the PLL. The PLL includes a voltage-controlled oscillator (VCO)
100
, a phase and frequency detector
102
, and a feedback frequency divider
104
. The VCO
100
often takes a voltage
106
as its control input and outputs a signal
108
whose frequency is based on the value of the input voltage
106
. The phase and frequency detector
102
operates in reverse. It takes two signals
109
,
110
as its inputs and outputs a voltage
106
based on the difference between the frequencies of the two signals
109
,
110
.
A PLL in a computer system, for example, receives a reference frequency source
110
, such as an external bus clock, and a feedback frequency
109
from the VCO as inputs to the phase and frequency detector
102
. The feedback signal
109
frequency is the VCO output frequency divided by the feedback frequency divider
104
. The output from the phase and frequency detector
102
is then used to control the VCO
100
. When the PLL is locked, the frequency and phase of the reference signal
110
and of the feedback signal
109
are equal. The VCO output
108
frequency is N times the frequency of the reference signal
110
(N is the dividing ratio of the feedback frequency divider
104
). If the VCO
100
starts to drift, the phase and frequency detector
102
detects and corrects the discrepancy.
The output of the PLL circuit can then be used to clock a processor, such as a central processing unit (CPU). Due to the feedback frequency divider
104
, the CPU clock has a significantly higher frequency than the bus clock.
In a preferred design for the PLL, charge pumps and a loop filter are coupled between the frequency comparator
102
and the VCO
100
to control the VCO output frequency. The charge pumps feed pulses of current to a capacitor in the loop filter. The current pulse charges and discharges the loop filter capacitor.
SUMMARY
A loop filter in the phase-locked loop includes a capacitor having a first capacitance. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier amplifies a signal at the node in a way that increases the first capacitance without physically changing the capacitor.


REFERENCES:
patent: 4524333 (1985-06-01), Iwata et al.
patent: 4682116 (1987-07-01), Wolaver et al.
patent: 5021749 (1991-06-01), Kasai et al.
patent: 5170130 (1992-12-01), Ichihara
patent: 5382918 (1995-01-01), Yamatake
patent: 5479126 (1995-12-01), Pan et al.
patent: 6057739 (2000-05-01), Crowley et al.
patent: 6344772 (2002-02-01), Larsson
patent: 6389092 (2002-05-01), Momtaz

Affiliated with

Also associated with

Rating

Adaptive integrated PLL loop filter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adaptive integrated PLL loop filter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive integrated PLL loop filter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3062373