Adaptive integrated circuit design simulation transistor...

Details Adaptive integrated circuit design simulation transistor... Adaptive integrated circuit design simulation transistor...

1999-06-14

2002-05-28

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S022000, C716S030000

Reexamination Certificate

active

06397172

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of simulating integrated circuit (IC) designs. More specifically, the present invention relates to model evaluations performed during simulation.
2. Background Information
Circuit simulation involves taking a description of a circuit usually called a netlist, and a description of the input stimulus and then solving certain mathematical equations to determine the response of the circuit to the given input stimulus over the simulation time period. An example of a circuit simulator is the SPICE simulator, originally developed by W. Nagel. See e.g. W. Nagel, “SPICE2, A computer program to simulate semiconductor circuits”, University of California, Berkeley, Memo No. ERL-M520, May 1975. Circuit simulators like SPICE represent a circuit as a set of coupled first order non-linear differential equations. Well-known techniques like Modified Nodal Analysis are used to perform this mathematical representation. The set of coupled non-linear equations is then solved using a sequence of steps, as illustrated in FIG.
7
. The steps involve determining the time-step of integration, linearising the differential equations, and solving the resulting set of linear algebraic equations. The process is repeated till convergence is reached. Once convergence has been achieved, time is advanced and the entire process is repeated.
This traditional method of circuit simulation has a time complexity of O(N
3
) in the worst case and O(N
1.5
) in the average case. This is due to the step involving the solution of the linear algebraic equations. This solution requires solving a matrix which has the time complexity of O(N
3
). Due to this super-linear time complexity of the algorithm in circuit simulators like SPICE, they are incapable of solving large circuits. Usually the limits of such simulators are reached when circuit sizes reach 100,000 devices. Solving circuits larger than this size becomes impossible since the time taken to find the solution becomes very large.
The need to solve large circuits is becoming ever more important due to the advances of silicon process technology. Integrated circuits or chips with multimillion transistors are quite common. In order to address this need, alternative algorithms have been developed. For example, algorithms developed by C. X Huang etc, as disclosed in C. X. Huang et al., “The design and implementation of Powermill”, Proceedings of the International Symposium on Low Power Design, pp. 105-120, 1995, by Y.-H. Shih etc as disclosed in Y. H. Shin et al., “ILLIADS: A new Fast MOS Timing Simulator Using Direct Equation Solving Approach” Proceedings of 28
th
ACM/IEEE Design Automation Conference, 1991, and by A. Devgan as disclosed in A. Devgan, “Transient Simulation of Integrated Circuits in the Charge-Voltage Plane”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VI. 15, No. 11, November 1996. These algorithms are characterized by a linear O(N) time complexity, thereby allowing them to handle large circuits.
The linear time complexity in these algorithms is achieved by partitioning the circuit into small partitions. To avoid the super-linear time of matrix solution, these algorithms use an approximate (i.e. inaccurate) solution instead. Under Huang's approach, an algorithm called one-step relaxation is used. This algorithm often has inaccuracies of up to 20% and has serious problems on stiff circuits. In common circuits, relaxation based algorithms do not obtain the correct results. Circuits characterized by tight feedback or coupling cause problems for these algorithms. Under Shih's approach, a direct equation solving technique is used; this works well in very limited situations where the device models can be accurately modeled by the second-order Shichman and Hodges model. This is rarely true with the latest silicon process technologies that require the very complex and highly non-linear BSIM3 models for accurate device models. Devgan uses an explicit integration technique but as evidenced from the waveforms in this paper, the accuracy is inadequate. The common problem with using any approximate algorithm for solving the matrix equations is that accuracy is usually not consistently good for all circuit design styles, especially for stiff circuits.
Standard matrix based algorithms do not suffer from the inaccuracy of relaxation and other approximate algorithms. Using matrix based algorithms along with partitioning can result in good accuracy; only the nodes at the boundaries of partitions can have degraded accuracy. However, use of single time-step for all partitions produces significantly reduced performance. Furthermore, in evaluating transistor models, numerous capacitance and derivative voltage values are required in solving the equations.
Thus, an improved approach to circuit simulation is desired.
SUMMARY OF THE INVENTION
An IC design computer simulation tool is provided with a design reader equipped to assign device characterizations to electronic devices of an IC design, and model evaluators equipped to adaptively perform model evaluations in accordance with the electronic devices' assigned device characterizations. In one embodiment, the electronic devices include transistors, and the adaptive model evaluations provide evaluated model quantities to support solution of the circuit node voltages using fully coupled (implicit) or partially coupled (explicit) solution techniques. In particular, the transistor capacitive coupling currents are expressed according to the assigned device characterizations.


REFERENCES:
patent: 5553008 (1996-09-01), Huang et al.
Dhar et al, “Current and Charge Estimation in CMOS Circuits”, Proceedings of the Conference on Asia Pacific Design Automation Conference (CD-ROM), pp. 13-18 (Sep. 1995).*
Stein et al, “ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits”, Proceedings of the 28th ACM/IEEE Design Automation Conference, pp. 26-31 (Jun. 1991).*
Kao et al, “Timing Analysis for Piecewise Linear Rsim”, IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 13 Issue 12, pp. 1498-1512 (Dec. 1994).*
Devgan, A., “Transient Simulation of Integrated Circuits in the Charge-Voltage Plane,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 1996, IEEE, USA, vol. 15, No. 11, pp. 1379-1390.
Devgan, A., et al., “Adaptively Controlled Explicit Simulation,” IEEE Transactions on Computer Aided Design on Integrated Circuits and systems, Jun. 1994, vol. 13, No. 6, IEEE Inc., New York, US pgs. 746-762.

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