Adaptive instruction processing by array processor having proces

Details Adaptive instruction processing by array processor having proces Adaptive instruction processing by array processor having proces

1986-03-13

1988-11-08

Shaw, Gareth D.

Boots, shoes, and leggings

382 49, G06F 1500

Patent

active

047837381

ABSTRACT:
Equipping individual processing elements with an instruction adapter provides an array processor with adaptive spatial-dependent and data-dependent processing capability. The instruction becomes variable, at the processing element level, in response to spatial and data parameters of the data stream. An array processor can be optimized, for example, to carry out very different instructions on spatial-dependent data such as blank margin surrounding the black lines of a sketch. Similarly, the array processor can be optimized for data-dependent values, for example to execute different instructions for positive data values than for negative data values. Providing each processing element with a processor identification register permits an easy setup by flowing the setup values to the individual processing elements, together with setup of condition control values. Each individual adaptive processing element responds to the composite values of original setup and of the data stream to derive the instruction for execution during the cycle. In the usual operation, each adaptive processing element is individually addressed to set up a base instruction; it also is conditionally set up to execute a derived instruction instead of the base instruction. An array processor made up of adaptive processing elements can adapt dynamically to changes in its input data stream, and thus can be dynamically optimized, resulting in greatly enhanced performance at very low incremental cost.

REFERENCES:
patent: 3287702 (1986-11-01), Borck, Jr. et al.
patent: 3287703 (1986-11-01), Slotnick
patent: 3544973 (1970-12-01), Borck, Jr. et al.
patent: 3970993 (1976-07-01), Finnila
patent: 4187539 (1980-02-01), Eaton
patent: 4287566 (1981-09-01), Culler
patent: 4301443 (1981-11-01), Sternberg et al.
patent: 4344134 (1982-08-01), Barnes
patent: 4380046 (1983-04-01), Fung
patent: 4398176 (1983-08-01), Dargel et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4464689 (1984-08-01), Sternberg
patent: 4467409 (1984-08-01), Potash et al.
patent: 4484346 (1984-11-01), Sternberg et al.
patent: 4541116 (1985-09-01), Lougheed
patent: 4558411 (1985-12-01), Faber et al.
patent: 4574394 (1986-03-01), Holsztynski et al.
Fountain, T. J., "Towards Clip 6-An Extra Dimension", IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Nov. 1981, pp. 25-30.
U.S.S.R. Author's Certificate No. 83-721416/30, Associative Processors Microprogram Control Apparatus, Tbilisi Elva Combin, Sep. 15, 1982.
Davis et al, Systolic Array Chip Matches the Pace of High-Speed Processing, Electronic Design, Oct. 31, 1984, pp. 207-218.
NCR Geometric Arithmetic Parallel Processor, product specification NCR45CG72, NCR Corp., Dayton, Ohio, 1984, pp. 1-12.
Cloud et al, High Efficiency for Parallel Processors, IEEE Southcon, reprint published by NCR Corporation Microelectronics Div. Fort Collins, CO, pp. 1-7.
J. L. Potter, Image Processing on the Massively Parallel Processor, Computer, vol. 16, No. 1, pp. 62-67.
Masatsugu Kidode, Image Processing Machines in Japan, Computer, vol. 16, No. 1, pp. 68-80.
Stanley R. Sternberg, Biomedical Image Processing, Computer, vol. 16, No. 1, pp. 22-34.
Kai Hwang and King-sun Fu, Integrated Computer Architectures for Image Processing and Database Management, Computer, vol. 16, No. 1, pp. 51-60.
Kendall Preston, Jr., Cellular Logic Computers for Pattern Recognition, Computer, vol. 16, No. 1, pp. 36-47.
Azriel Rosenfeld, Parallel Image Processing Using Cellular Arrays, Computer, vol. 16, No. 1, pp. 14-20.
The TTL Data Book for Design Engineers, Second Edition, Texas Instruments Inc. Bulletin No. DL-S 7712350, pp. 7-471, Bulletin No. DL-S 7611866, pp. 7-316, Bulletin No. DL-2 7711847, pp. 7-181.

Affiliated with

Also associated with

Rating

Adaptive instruction processing by array processor having proces does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adaptive instruction processing by array processor having proces, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive instruction processing by array processor having proces will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-466464