Adaptive frequency synthesizer with synchronization

Details Adaptive frequency synthesizer with synchronization Adaptive frequency synthesizer with synchronization

1996-09-23

2000-05-23

Heckler, Thomas M.

Pulse or digital communications

Repeaters

Testing

375362, 395807, G06F 112

Patent

active

060674113

ABSTRACT:
The present invention pertains to a clock generator that provides a plurality of dock outputs, each of which can be synchronized from one of several possible sets of references. Multiple frequency synthesizers are used to generate the clocks at the desired frequencies. These frequency synthesizers operate on the principle of dividing a supplied reference dock by an integer (I), plus a ratio (R/M), whereby there are approximately I plus (R/M) input clock cycles per output clock cycle. The output of a frequency synthesizer is a train of pulses with its duration equal to the period of the reference clock and at a rate equal to N/D=1/(I+R/M) times the reference clock rate. In order to generate an output signal with a more uniform duty cycle, the pulse train drives a toggle select circuit. The function of the toggle select circuit is to remove half of the phase quantization due to the limited frequency resolution of the reference dock. This is accomplished by selecting between the rising edge output of the toggle versus a falling edge delayed version of that same signal.

REFERENCES:
patent: 5473274 (1995-12-01), Reilly et al.
patent: 5481697 (1996-01-01), Mathews et al.
patent: 5534939 (1996-07-01), Nakamura et al.
patent: 5546434 (1996-08-01), Kalafatis
patent: 5668830 (1997-09-01), Georgiou et al.

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