Adaptive frame resynchronizer apparatus

Details Adaptive frame resynchronizer apparatus Adaptive frame resynchronizer apparatus

1990-01-08

1991-10-08

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

375108, 375107, 3701051, H04L 706, H04J 306

Patent

active

050561197

ABSTRACT:
A frame synchronization circuit is illustrated, which uses an algorithm of reverting to an initial state of selecting the next logic zero data bit in a data bit stream for the potential bit position to be used as a framing bit, and returning to reinitialization if any of the next M-bits in that bit position do not follow a prescribed framing pattern. Once synchronization is established, the detection of three out of five framing bits being in error will cause the circuit to return to an intermediate state in the framing process, whereby any further errors in the next X number of bits will cause reinitialization, but the lack of any further errors in the next X-bits will allow the circuit to confirm that its original bit position choice as framing bit was correct. This allows the circuit to continue operation with the assurance that it is correctly synchronized with the data, and without interrupting data flow for the comparatively long time it takes to synchronize from "scratch".

REFERENCES:
patent: 4763324 (1988-08-01), Schwierz
patent: 4768192 (1988-08-01), Pattavina et al.
patent: 4788681 (1988-11-01), Thomas et al.
patent: 4794626 (1988-12-01), Tanabe et al.

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