Television – Format conversion – Line doublers type
Reexamination Certificate
1999-11-05
2003-04-01
Hsia, Sherrie (Department: 2614)
Television
Format conversion
Line doublers type
C348S452000
Reexamination Certificate
active
06542196
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to de-interlacing systems generally and, more particularly, to a system for enabling adaptive field pairing based on predetermined, user defined, and/or auto-calibrated de-interlacing parameters.
BACKGROUND OF THE INVENTION
De-interlacing is necessary to display interlaced source material on a progressive-only display. Also, de-interlacing can remove or reduce interlacing artifacts. Most televisions are interlaced for historic and bandwidth saving reasons, sending fields every 60th of a second, where two fields make up a frame. Most computer monitors are progressive, sending frames every 60th of a second, depending on the particular refresh rate implemented.
Referring to
FIG. 1
, an example of a conventional de-interlacing system is shown. The system
10
generally comprises a source decoder
12
, an encoder
14
, an encoder
16
, a circuit
18
. The circuit
18
may present signals to an SVGA connector
20
. The SVGA connector
20
is connected to a progressive monitor
22
that can display 60 frames per second. The encoder
14
presents either a composite signal, an S-video signal or an RGB signal. The composite, S-video or RGB signal is presented to an interlaced monitor
24
. The encoder
16
presents either a composite, an S-video or an RGB signal to an interlaced monitor
26
. Additionally, the RGB signal is presented to a progressive monitor
28
. The circuit
18
includes a line doubler
30
and a RGB conversion circuit
32
. The circuit
18
is an SVGA controller.
Referring to
FIG. 2
, an example of a next generation decoder
50
is shown. The decoder
50
comprises a decoder portion
52
and an encoder portion
54
. The encoder
54
is an NTSC/PAL encoder with integrated digital-to-analog conversion and RGB outputs.
Referring to
FIG. 3
, a conventional method for presenting various screen formats is shown. A frame storage circuit
60
stores a variety of frames in a 4:2:0 format. A host controller
62
via the channel, presents a MPEG2 sequencing picture header for vertical resolution, horizontal resolution, pictures/second, aspect ratio and programming/interlacing. A display controller
64
includes a vertical filter
66
, a horizontal decimal filter
68
and a horizontal filter
70
.
Referring to
FIG. 4
, a conventional display controller implementing progressive and interlaced handling is shown. A field is sent every {fraction (1/60)}th of a second to an NTSC encoder. The NTSC encoder is programmed for interlacing only. The progressive frame is normally implemented as a SIF, such that the first
240
lines are presented to each field. SIF is Source Input Format, a derivative of the CCIR
601
format for video frames. The interlace frame is made up of two×240 line fields with temporal displacement. The host controller enables parsing of the sequence header of an MPEG bit stream for (i) vertical resolution, (ii) horizontal resolution, (iii) pictures/second, (iv) 4:3 or 16:9 aspect ratio selection, and (v) progressive or interlaced, (in picture header also). An MPEG1 bitstream is always progressive, SIF, 1.5 Mb/sec, and 4:2:0. An MPEG2 bitstream is progressive or interlaced, frame pictures, field pictures or 2-field pictures.
The various conventional de-interlacing methods shown in
FIGS. 1-4
each require one or more of the following (i) adding the odd and even fields together to create a progressive frame; (ii) choosing either a first field or a second, double the number of lines, and using the combination as a progressive frame; (iii) vertical filtering nearby lines to create a missing line; (iv) vertical temporal filtering (this is (iii) plus temporal filtering from adjacent fields); (v) adaptive motion compensation (i.e., using the current field compared to the previous first or second fields on a pixel by pixel basis); and (vi) traditional adaptive field pairing (i.e., if no motion-field merge, if motion-vertical temporal filtering of entire frame).
The disadvantages with conventional de-interlacing methods (i) is if there is movement between the fields, jagged edges may result; (ii) is use of only one-half the vertical information available, if 30 frames/sec, or if 60 frames/sec, flicker can occur since there are fill lines, (iii, iv, v) is lack of use of field merge, and (vi) is visible switching between types, especially around the motion threshold.
SUMMARY OF THE INVENTION
One aspect of the present invention concerns a method for de-interlacing a decoded video stream comprising the steps of (A) defining a sampling period, (B) sampling the decoded video stream during the sampling period to define one or more parameters, (C) adjusting a threshold and a level of the decoded video stream used in processing, in response to the one or more parameters, (D) filtering the decoded video stream using a filter tool selected from a plurality of filters, in response to the one or more parameters.
Another aspect of the present invention concerns a method for de-interlacing a decoded video stream having a plurality of frames comprising the steps of (A) comparing a first one of the plurality of frames with a next one of the plurality of frames, (B) if the first frame and the next frame are within a predetermined criteria, simultaneously displaying the first frame and the next frame as a progressive frame and (C) if the first frame and the next frame are not within a predetermined criteria, filtering the next frame.
The objects, features and advantages of the present invention include providing a de-interlacing system that may implement (i) user defined de-interlacing parameters, (ii) auto-calibration of de-interlacing, (iii) auto-calibration that may be re-done at programmed points in the video stream or at points after which some parameter has been achieved (e.g., eight fields in a row with maximum number of pixel deltas), (iv) extensive de-interlacing parameter options, (v) user defined or auto-calibration gauges as to when to vertically filter or not vertically filter the rest of the group, (vi) “softer” tap filtering at boundaries of vertically filtered and not vertically filtered groups, and/or (vii) an encoder that may be enabled to provide information in interlaced fields that enable low-cost, accurate, de-interlacing at the decoder.
REFERENCES:
patent: 6118488 (2000-09-01), Huang
patent: 6269484 (2001-07-01), Simsic et al.
patent: 6348949 (2002-02-01), McVeigh
Hsia Sherrie
LSI Logic Corporation
Maiorana PC Christopher P.
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