Adaptive equalizing circuit

Details Adaptive equalizing circuit Adaptive equalizing circuit

2000-11-15

2002-05-07

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Equalizers

Automatic

C708S323000

Reexamination Certificate

active

06385239

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an adaptive equalization circuit implemented by a digital circuit and, more particularly, to an adaptive equalization circuit that is suitable for equalization of a non-linear signal, and performs high-order partial response equalization so that an equalization error of a reproduced signal having non-linear distortions is minimized when reproducing it from a high-density recording medium, thereby improving the characteristics of the reproduced signal.
BACKGROUND ART
In an apparatus for recording and reproducing data in/from recording media, reproduction of data is carried out without being affected by non-linear distortions, by using a method of detecting non-linear distortions from a waveform and correcting the waveform with an equalizer to remove the non-linear distortions, or a method of controlling the slice level of maximum likelihood decoding.
That is, in the recording/playback apparatus, when the reproduced signal has a waveform with non-linear distortions, an adaptive equalization method is employed, in which the distortions of the waveform are estimated from the reproduced signal to decide the characteristics of the equalizer. To be specific, filter coefficients of the equalizer are optimized so that the second power error between the level after the equalization and the original level of the reproduced signal is minimized.
Further, when equalizing the reproduced signal during playback of recorded data from the recording medium, partial response equalization is employed to suppress enhancement of the high frequency band components of the reproduced signal characteristics and to prevent the error rate from being increased due to noise.
The partial response equalization is a method of provisionally deciding multiple values by appropriately controlling the quantity of interference between codes in a signal, and restricting the signal power with respect to the frequency instead of the decision.
That is, a target signal to be equalized and a signal obtained by delaying the target signal are superposed to make the multi-valued levels easy to appear, and the signal is decoded by performing provability calculation using a Viterbi decoder or the like. Thereby, the levels of the signal are easily detected without using the high frequency band components of the signal.
A conventional equalizer performing such partial response equalization has the following characteristics. That is, when the equalizer receives a reproduced signal from a portion corresponding to an edge of a recording pit of an optical magnetic recording medium or a portion where the direction of vertical magnetization is inverted, it equalizes the reproduced signal to an equalization target value. Therefore, equalization to the target value is not compulsory performed on a portion of the waveform amplitude where the codes are continuous, excluding the both edges of the portion, and thus the high frequency components included in the reproduced signal are prevented from being emphasized unnecessarily, whereby the noise included in the input signal of the equalizer is prevented from being transmitted to the output signal of the equalizer.
Further, when the characteristics of the reproduced signal vary, the SN ratio of the output signal from the equalizer can be maintained by adaptively controlling the characteristics of the equalizer.
This equalizer uses only its output corresponding to the code-inverted portion of the reproduced waveform of the optical disk as a signal for controlling tap coefficients of the equalizer, and adaptively controls the tap coefficients so that the output from the equalizer is partial-response-equalized.
An example of a conventional equalizer as described above is shown in FIG.
2
.
An adaptive equalizer shown in
FIG. 2
is one disclosed in, for example, Japanese Published Patent Application No. Hei. 8-153370, and this equalizer detects a position corresponding to a pit edge of a reproduced signal or a portion where the direction of magnetization is inverted in vertical magnetic recording, and performs equalization to predetermined reference amplitudes {−1,0,+1} at the detected position. Reference amplitudes corresponding to other positions than mentioned above are not defined.
This equalizer has three values “−1”, “0”, and “+1” as reference amplitudes. In
FIG. 2
,
27
denotes an input terminal for receiving a signal to be subjected to waveform equalization, and
12
a,
12
b,
and
12
c
denote delay means which are connected in series in this order, and each delay means delays its input signal by one unit time T. The signal outputted from the input terminal
27
is applied to the delay means
12
a.
Further,
25
a,
25
b,
and
25
c
denote correlators for correlating the output signals from the delay means
12
a,
12
b,
12
c
with an output signal from a switch
24
described later, respectively. Further,
26
a,
26
b,
and
26
c
denote integrators for integrating the output signals from the correlators
25
a,
25
b,
and
25
c,
respectively.
Further,
20
denote a transversal equalization circuit. In the transversal equalization circuit
20
,
12
d
and
12
e
denote delay means which are connected in series in this order, and each delay means delays its input signal by one unit time T. The signal outputted from the input terminal
27
is applied to the delay means
12
d.
Further,
16
a,
16
b,
and
16
c
denote buffers as multipliers. These buffers
16
a,
16
b,
and
16
c
receive, as control signals, the output signals from the integrators
26
a,
26
b,
and
26
c,
and receive, as input signals, the input signal to the delay means
12
d,
the output signal from the delay means
12
d,
and the output signal from the delay means
12
e,
respectively.
14
a
denotes an adder for adding the output signals from the buffers
16
a
and
16
b,
and
14
b
denotes an adder for adding the output signals from the adder
14
a
and the buffer
16
c.
Furthermore,
28
denotes an output terminal for outputting the output signal from the adder
14
b,
that is, the signal which has been subjected to waveform equalization by the adaptive equalizer;
21
denotes a ternary decision circuit for subjecting the signal R from the output terminal
28
to ternary decision;
22
denotes a reference amplitude generation circuit for generating a signal D having a reference amplitude on the basis of the output signal from the ternary decision circuit
21
;
17
denotes a subtracter for subtracting the signal R at the output terminal
28
from the output signal D of the reference amplitude generation circuit
22
;
29
denotes a delay circuit for delaying an error signal E
1
outputted from the subtracter
17
by one unit time T;
24
denotes a switch for disconnecting the output of the delay circuit
29
and generating an error signal E
2
to be supplied to the correlators
25
a,
25
b,
and
25
c;
and
23
denotes an error signal selection circuit for outputting a selection signal S for controlling the switch
24
, on the basis of the output from the ternary decision circuit
21
.
Next, the operation will be described. The signal, which is obtained by subjecting the output signal R from the transversal equalization circuit
20
to ternary decision by the ternary decision circuit
21
, is converted to a ternary signal D having a reference amplitude by the reference amplitude generation circuit
22
. The output signal R and the ternary signal D are input to the subtracter
17
, and an output error signal E
1
is taken out.
The error signal selection circuit
23
extracts, from the output signal of the ternary decision circuit
21
, the timing at which an effective error signal is output, and outputs a selection signal S. The switch
24
is operated by the selection signal S so as to send only the effective error signal as a reference error signal E
2
to the correlator
25
. When the selection signal S becomes active, the switch
24
is closed, whereby the input E
2
to the correlator becomes equal to E
1
. As a result, t

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