Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1999-11-02
2003-07-01
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C375S233000, C375S234000, C375S236000, C375S341000, C379S392000, C379S413020
Reexamination Certificate
active
06587504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an adaptive equalizer correcting a filter coefficient (tap coefficient) for an input signal so as to minimize the error between an output signal and a reference signal. Particularly, the present invention relates to an adaptive equalizer that can reduce the delay time of a critical path, and a method of designing that adaptive equalizer.
2. Description of the Background Art
In the field of cable television service (CATV) and the like, the usage of digital communication that employs digital signals impervious to noise instead of analog signals is now practically in progress as a high speed data communication system replacing the conventional analog communication. The presence of multiple delay waves arising from multipath propagation caused by wave reflection at the end of a non-terminated cable has been ascertained in the digital cable television service. The presence of such multiple delay waves causes multiple wave fading due to the interference between the main wave and the delay waves. When the amplitude of a delay wave approximates to that of the main wave, frequency selective fading occurs in which a particular frequency component is attenuated significantly, to result in generation of waveform distortion. This waveform distortion may induces code error by inter-symbol interference. It is necessary to prevent generation of frequency selective fading caused by such multiple delay waves in high speed digital transmission.
An adaptive equalizer that adaptively removes inter-symbol interference arising from multipath propagation has been studied as one technique to solve this frequency selective fading. In digital communication, data referred to as “symbol” is transmitted at every predetermined period referred to as “symbol cycle”. In an ideal transmission path free from multipath propagation, one symbol will not affect another symbol transmitted at another symbol cycle. However, when multiple delay waves are generated by multipath propagation, a plurality of symbols will arrive at the reception side in the same symbol cycle by the delay waves. More specifically, inter-symbol interference occurs to disable proper reception and reproduction of transmitted signals.
The above-described problem of frequency selective fading occurs, not only in wire communication utilizing a cable, but also in wireless transmission paths utilizing microwaves.
The LMS (Least Mean Square Error Algorithm) architecture is often employed for the adaptive equalizer used in digital communication. The basic structure of this LMS architecture includes an FIR (Finite Impulse Response) filter.
FIG. 11
shows the basic structure of a conventional adaptive equalizer. This adaptive equalizer includes a filter processing unit
1
applying a filtering process on an input signal x(n), an error detection circuit
2
obtaining an error between an output signal y(n) of filter processing unit
1
and a reference signal d(n), and a coefficient update circuit
3
correcting tap coefficients (filter coefficients) h
0
~hN−1 of filter processing unit
1
according to an output signal e(n) of error detection circuit
2
.
Filter processing unit
1
is formed of a direct type discrete filter. A discrete input signal x(n) extracted from the response characteristics at the time region is filtered according to tap coefficients h
0
~hN−1, to produce a discrete output signal y(n). Reference signal d(n) is output from an identification circuit (or determination circuit) that estimates a final output signal (code) from output signal y(n) of filter processing unit
1
.
Discrete filter
1
includes delay elements SR
0
~SRN−1 connected in series and each formed of a shift register delaying input signal x(n) by one clock cycle period, multipliers M
0
~MN−1 multiplying the output signals of delay elements SR
0
~SRN−1 by corresponding tap coefficients h
0
~hN−1, and adders A
1
~AN−1 provided corresponding to multipliers M
1
~MN−1, respectively, for adding the output signals of preceding adders with the output signals of corresponding multipliers to transmit the addition result to succeeding adders. Output signal y(n) is generated from the last stage adder AN−1. Here, the output nodes of delay elements SR
0
~SRN−1 are generally referred to as “taps”. Therefore, direct filter
1
is an N-tap filter. As to “Z
−1
” of delay elements SR
0
~SRN−1, the exponent indicates the amount of delay.
Error detection circuit
2
is generally formed by an adder. Output signal y(n) is subtracted from reference signal d(n). That difference value is output as the error caused by frequency selective fading.
Coefficient update circuit
3
includes a multiplier Me multiplying error signal e(n) by step size &mgr;, and tap coefficient update stages provided corresponding to tap coefficients h
0
~hN−1, respectively. The tap coefficient update stages have the same structure, and each include a delay element CSR (CSR
0
~CSRN−1) formed of a shift register that delays the signal from the preceding stage by one clock cycle, a multiplier CM (CM
0
~CMN−1) multiplying an output signal &mgr;·e(n) of multiplier Me by the output signal of a corresponding delay element, an adder CA (CA
0
~CAN−1) receiving the output signal of multiplier CM, and a delay element CSF (CSF
0
~CSFN−1) formed of a shift register that delays the output signal of adder CA by one clock cycle. The output signal of delay element CSF is applied to adder CA. Adder CA adds the output signal of a corresponding multiplier CM with the output signal of a corresponding delay element CSF to provide the addition result to delay element CSF again.
Step size &mgr; indicates the step size of a discrete value of discrete input signal x(n) to normalize the error signal by multiplier Me. This step size is generally a multiple of 2. Multiplier Me is formed of a bit shift circuit that shifts error signal e(n) towards the higher bit in order to multiply error signal e(n) by step size &mgr; represented by 2 raised to the power. The operation of the adaptive equalizer shown in
FIG. 11
will be described now.
Each of delay elements SR
0
~SRN−1, CSF
0
~CSFN−1, and CSR
0
~CSRN−1 carries out a shift operation according to a clock signal not shown to implement delay of one clock cycle. Output signal y(n) of filter processing unit
1
is related to input signal x(n) by the following equation.
y
(
n
)=&Sgr;
hk·x
(
n−k
)
The summation is taken from 0 to N−1 for k. Error signal e(n) is represented by the difference between reference signal d(n) and output signal y(n). Therefore, the following equation is obtained.
&AutoLeftMatch;
e
(
n
)
=
d
(
n
)
-
y
(
n
)
=
d
(
n
)
-
∑
h
k
·
x
(
n
-
k
)
=
d
(
n
)
-
h
T
(
n
)
·
X
(
n
)
where h
T
(n)=[h
0
(n), h
1
(n), . . . , hn−1(n)],
X
T
=[x(n), x (n−1), . . . , x (n−N+1)], and
T represents transposition.
The tap coefficient of the next cycle is related to the tap coefficient of the current cycle by the following equation.
h
(
n
+1)=
h
(
n
)+&mgr;·
e
(
n
)·
X
(
n
)
One tap coefficient hk is corrected according to the following equation.
hk
(
n
+1)=
hk
(
n
)+&mgr;·
e
(
n
)·
x
(
n−k
)
In the above equation, the output signals of shift registers (delay element) SR
0
and CSR
0
of the first input stage shown in
FIG. 11
are set as x(n).
By correcting filter coefficients h
0
~hN−1 according to error signal e(n), the error component included in output signal y(n) may be removed to provide a more ideal output signal y(n).
In the adaptive equalizer shown in
FIG. 11
, the direct filter of filter processing unit
1
is formed of an FIR filter (non-recursive filter). Delay elements SR
0
~SRN−1 each are a shift register transferring a signal according to a clock signal not shown. It is necessar
Machida Hirohisa
Mizutani Hiroyuki
Murakami Shuji
Ochi Hiroshi
Ahn Sam
Chin Stephen
McDermott & Will & Emery
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