Adaptive equalizer

Pulse or digital communications – Equalizers – Automatic

Reexamination Certificate

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Details

C375S233000, C375S229000, C333S018000

Reexamination Certificate

active

07577193

ABSTRACT:
Some embodiments of the invention include apparatus, systems, and methods to adjust a clock generator and an equalizer to reduce jitter in an output signal. A phase detector provides feedback information on a first feedback loop and a second feedback loop. A clock adjustment circuit uses the feedback information on the first feedback loop to adjust a clock generator. An equalizer adjustment circuit uses the feedback information on the second feedback loop to adjust the equalizer. Other embodiments are described and claimed.

REFERENCES:
patent: 5132926 (1992-07-01), MacEachern et al.
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5321723 (1994-06-01), Mizoguchi
patent: 5841602 (1998-11-01), Kanegae et al.
patent: 5905769 (1999-05-01), Lee et al.
patent: 6055269 (2000-04-01), Drost et al.
patent: 2002/0122443 (2002-09-01), Enam et al.
patent: 2005/0074070 (2005-04-01), Betts
patent: 2005/0135470 (2005-06-01), Momtaz

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